up3_clock.tan.qmsg

来自「在UP3开发板上已经验证过的VHDL代码。 精确到十分之一秒」· QMSG 代码 · 共 14 行 · 第 1/4 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 28 15:35:51 2008 " "Info: Processing started: Wed May 28 15:35:51 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off UP3_CLOCK -c UP3_CLOCK --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off UP3_CLOCK -c UP3_CLOCK --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK_48MHZ " "Info: Assuming node \"CLK_48MHZ\" is an undefined clock" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 8 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_48MHZ" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}