up3_clock.hier_info

在UP3开发板上已经验证过的VHDL代码。 精确到十分之一秒

|UP3_CLOCK
reset => comb~0.IN0
reset => LCD_RW~reg0.ACLR
reset => LCD_RS~reg0.ACLR
reset => LCD_E~reg0.PRESET
reset => DATA_BUS_VALUE[0].ACLR
reset => DATA_BUS_VALUE[1].ACLR
reset => DATA_BUS_VALUE[2].ACLR
reset => DATA_BUS_VALUE[3].PRESET
reset => DATA_BUS_VALUE[4].PRESET
reset => DATA_BUS_VALUE[5].PRESET
reset => DATA_BUS_VALUE[6].ACLR
reset => DATA_BUS_VALUE[7].ACLR
reset => BCD_TSEC[0].ACLR
reset => BCD_TSEC[1].ACLR
reset => BCD_TSEC[2].ACLR
reset => BCD_TSEC[3].ACLR
reset => BCD_SECD0[0].ACLR
reset => BCD_SECD0[1].ACLR
reset => BCD_SECD0[2].ACLR
reset => BCD_SECD0[3].ACLR
reset => BCD_SECD1[0].ACLR
reset => BCD_SECD1[1].ACLR
reset => BCD_SECD1[2].ACLR
reset => BCD_SECD1[3].ACLR
reset => BCD_MIND0[0].ACLR
reset => BCD_MIND0[1].ACLR
reset => BCD_MIND0[2].ACLR
reset => BCD_MIND0[3].ACLR
reset => BCD_MIND1[0].ACLR
reset => BCD_MIND1[1].ACLR
reset => BCD_MIND1[2].ACLR
reset => BCD_MIND1[3].ACLR
reset => BCD_HRD0[0].ACLR
reset => BCD_HRD0[1].ACLR
reset => BCD_HRD0[2].ACLR
reset => BCD_HRD0[3].ACLR
reset => BCD_HRD1[0].ACLR
reset => BCD_HRD1[1].ACLR
reset => BCD_HRD1[2].ACLR
reset => BCD_HRD1[3].ACLR
reset => count2[0].ACLR
reset => count2[1].ACLR
reset => count2[2].ACLR
reset => count2[3].ACLR
reset => count2[4].ACLR
reset => count2[5].ACLR
reset => count2[6].ACLR
reset => count2[7].ACLR
reset => count2[8].ACLR
reset => count2[9].ACLR
reset => count2[10].ACLR
reset => count2[11].ACLR
reset => count2[12].ACLR
reset => count2[13].ACLR
reset => count2[14].ACLR
reset => count2[15].ACLR
reset => PBSwitch3_flop2.PRESET
reset => PBSwitch3_flop1.PRESET
reset => count3[0].ACLR
reset => count3[1].ACLR
reset => count3[2].ACLR
reset => count3[3].ACLR
reset => count3[4].ACLR
reset => count3[5].ACLR
reset => count3[6].ACLR
reset => count3[7].ACLR
reset => count3[8].ACLR
reset => count3[9].ACLR
reset => count3[10].ACLR
reset => count3[11].ACLR
reset => count3[12].ACLR
reset => count3[13].ACLR
reset => count3[14].ACLR
reset => count3[15].ACLR
reset => PBSwitch2_flop2.PRESET
reset => PBSwitch2_flop1.PRESET
reset => count1[0].ACLR
reset => count1[1].ACLR
reset => count1[2].ACLR
reset => count1[3].ACLR
reset => count1[4].ACLR
reset => count1[5].ACLR
reset => count1[6].ACLR
reset => count1[7].ACLR
reset => count1[8].ACLR
reset => count1[9].ACLR
reset => count1[10].ACLR
reset => count1[11].ACLR
reset => count1[12].ACLR
reset => count1[13].ACLR
reset => count1[14].ACLR
reset => count1[15].ACLR
reset => PBSwitch1_flop2.PRESET
reset => PBSwitch1_flop1.PRESET
reset => CLK_COUNT_400HZ~20.OUTPUTSELECT
reset => CLK_COUNT_400HZ~21.OUTPUTSELECT
reset => CLK_COUNT_400HZ~22.OUTPUTSELECT
reset => CLK_COUNT_400HZ~23.OUTPUTSELECT
reset => CLK_COUNT_400HZ~24.OUTPUTSELECT
reset => CLK_COUNT_400HZ~25.OUTPUTSELECT
reset => CLK_COUNT_400HZ~26.OUTPUTSELECT
reset => CLK_COUNT_400HZ~27.OUTPUTSELECT
reset => CLK_COUNT_400HZ~28.OUTPUTSELECT
reset => CLK_COUNT_400HZ~29.OUTPUTSELECT
reset => CLK_COUNT_400HZ~30.OUTPUTSELECT
reset => CLK_COUNT_400HZ~31.OUTPUTSELECT
reset => CLK_COUNT_400HZ~32.OUTPUTSELECT
reset => CLK_COUNT_400HZ~33.OUTPUTSELECT
reset => CLK_COUNT_400HZ~34.OUTPUTSELECT
reset => CLK_COUNT_400HZ~35.OUTPUTSELECT
reset => CLK_COUNT_400HZ~36.OUTPUTSELECT
reset => CLK_COUNT_400HZ~37.OUTPUTSELECT
reset => CLK_COUNT_400HZ~38.OUTPUTSELECT
reset => CLK_COUNT_400HZ~39.OUTPUTSELECT
reset => CLK_400HZ~1.OUTPUTSELECT
reset => RESET_LED.DATAIN
reset => CLK_COUNT_10HZ[0].ENA
reset => CLK_COUNT_10HZ[1].ENA
reset => CLK_COUNT_10HZ[2].ENA
reset => CLK_COUNT_10HZ[3].ENA
reset => CLK_COUNT_10HZ[4].ENA
reset => CLK_COUNT_10HZ[5].ENA
reset => CLK_COUNT_10HZ[6].ENA
reset => CLK_COUNT_10HZ[7].ENA
reset => next_command~6.IN1
reset => state~45.IN1
CLK_48MHZ => count3[0].CLK
CLK_48MHZ => count3[1].CLK
CLK_48MHZ => count3[2].CLK
CLK_48MHZ => count3[3].CLK
CLK_48MHZ => count3[4].CLK
CLK_48MHZ => count3[5].CLK
CLK_48MHZ => count3[6].CLK
CLK_48MHZ => count3[7].CLK
CLK_48MHZ => count3[8].CLK
CLK_48MHZ => count3[9].CLK
CLK_48MHZ => count3[10].CLK
CLK_48MHZ => count3[11].CLK
CLK_48MHZ => count3[12].CLK
CLK_48MHZ => count3[13].CLK
CLK_48MHZ => count3[14].CLK
CLK_48MHZ => count3[15].CLK
CLK_48MHZ => PBSwitch3_flop2.CLK
CLK_48MHZ => PBSwitch3_flop1.CLK
CLK_48MHZ => count2[0].CLK
CLK_48MHZ => count2[1].CLK
CLK_48MHZ => count2[2].CLK
CLK_48MHZ => count2[3].CLK
CLK_48MHZ => count2[4].CLK
CLK_48MHZ => count2[5].CLK
CLK_48MHZ => count2[6].CLK
CLK_48MHZ => count2[7].CLK
CLK_48MHZ => count2[8].CLK
CLK_48MHZ => count2[9].CLK
CLK_48MHZ => count2[10].CLK
CLK_48MHZ => count2[11].CLK
CLK_48MHZ => count2[12].CLK
CLK_48MHZ => count2[13].CLK
CLK_48MHZ => count2[14].CLK
CLK_48MHZ => count2[15].CLK
CLK_48MHZ => PBSwitch2_flop2.CLK
CLK_48MHZ => PBSwitch2_flop1.CLK
CLK_48MHZ => count1[0].CLK
CLK_48MHZ => count1[1].CLK
CLK_48MHZ => count1[2].CLK
CLK_48MHZ => count1[3].CLK
CLK_48MHZ => count1[4].CLK
CLK_48MHZ => count1[5].CLK
CLK_48MHZ => count1[6].CLK
CLK_48MHZ => count1[7].CLK
CLK_48MHZ => count1[8].CLK
CLK_48MHZ => count1[9].CLK
CLK_48MHZ => count1[10].CLK
CLK_48MHZ => count1[11].CLK
CLK_48MHZ => count1[12].CLK
CLK_48MHZ => count1[13].CLK
CLK_48MHZ => count1[14].CLK
CLK_48MHZ => count1[15].CLK
CLK_48MHZ => PBSwitch1_flop2.CLK
CLK_48MHZ => PBSwitch1_flop1.CLK
CLK_48MHZ => ALARM_BCD_HRD1[0].CLK
CLK_48MHZ => ALARM_BCD_HRD1[1].CLK
CLK_48MHZ => ALARM_BCD_HRD1[2].CLK
CLK_48MHZ => ALARM_BCD_HRD1[3].CLK
CLK_48MHZ => ALARM_BCD_HRD0[0].CLK
CLK_48MHZ => ALARM_BCD_HRD0[1].CLK
CLK_48MHZ => ALARM_BCD_HRD0[2].CLK
CLK_48MHZ => ALARM_BCD_HRD0[3].CLK
CLK_48MHZ => ALARM_BCD_MIND1[0].CLK
CLK_48MHZ => ALARM_BCD_MIND1[1].CLK
CLK_48MHZ => ALARM_BCD_MIND1[2].CLK
CLK_48MHZ => ALARM_BCD_MIND1[3].CLK
CLK_48MHZ => ALARM_BCD_MIND0[0].CLK
CLK_48MHZ => ALARM_BCD_MIND0[1].CLK
CLK_48MHZ => ALARM_BCD_MIND0[2].CLK
CLK_48MHZ => ALARM_BCD_MIND0[3].CLK
CLK_48MHZ => TEMP_BCD_HRD1[0].CLK
CLK_48MHZ => TEMP_BCD_HRD1[1].CLK
CLK_48MHZ => TEMP_BCD_HRD1[2].CLK
CLK_48MHZ => TEMP_BCD_HRD1[3].CLK
CLK_48MHZ => TEMP_BCD_HRD0[0].CLK
CLK_48MHZ => TEMP_BCD_HRD0[1].CLK
CLK_48MHZ => TEMP_BCD_HRD0[2].CLK
CLK_48MHZ => TEMP_BCD_HRD0[3].CLK
CLK_48MHZ => TEMP_BCD_MIND1[0].CLK
CLK_48MHZ => TEMP_BCD_MIND1[1].CLK
CLK_48MHZ => TEMP_BCD_MIND1[2].CLK
CLK_48MHZ => TEMP_BCD_MIND1[3].CLK
CLK_48MHZ => TEMP_BCD_MIND0[0].CLK
CLK_48MHZ => TEMP_BCD_MIND0[1].CLK
CLK_48MHZ => TEMP_BCD_MIND0[2].CLK
CLK_48MHZ => TEMP_BCD_MIND0[3].CLK
CLK_48MHZ => TEMP_BCD_SECD1[0].CLK
CLK_48MHZ => TEMP_BCD_SECD1[1].CLK
CLK_48MHZ => TEMP_BCD_SECD1[2].CLK
CLK_48MHZ => TEMP_BCD_SECD1[3].CLK
CLK_48MHZ => TEMP_BCD_SECD0[0].CLK
CLK_48MHZ => TEMP_BCD_SECD0[1].CLK
CLK_48MHZ => TEMP_BCD_SECD0[2].CLK
CLK_48MHZ => TEMP_BCD_SECD0[3].CLK
CLK_48MHZ => CLK_400HZ.CLK
CLK_48MHZ => CLK_COUNT_400HZ[0].CLK
CLK_48MHZ => CLK_COUNT_400HZ[1].CLK
CLK_48MHZ => CLK_COUNT_400HZ[2].CLK
CLK_48MHZ => CLK_COUNT_400HZ[3].CLK
CLK_48MHZ => CLK_COUNT_400HZ[4].CLK
CLK_48MHZ => CLK_COUNT_400HZ[5].CLK
CLK_48MHZ => CLK_COUNT_400HZ[6].CLK
CLK_48MHZ => CLK_COUNT_400HZ[7].CLK
CLK_48MHZ => CLK_COUNT_400HZ[8].CLK
CLK_48MHZ => CLK_COUNT_400HZ[9].CLK
CLK_48MHZ => CLK_COUNT_400HZ[10].CLK
CLK_48MHZ => CLK_COUNT_400HZ[11].CLK
CLK_48MHZ => CLK_COUNT_400HZ[12].CLK
CLK_48MHZ => CLK_COUNT_400HZ[13].CLK
CLK_48MHZ => CLK_COUNT_400HZ[14].CLK
CLK_48MHZ => CLK_COUNT_400HZ[15].CLK
CLK_48MHZ => CLK_COUNT_400HZ[16].CLK
CLK_48MHZ => CLK_COUNT_400HZ[17].CLK
CLK_48MHZ => CLK_COUNT_400HZ[18].CLK
CLK_48MHZ => CLK_COUNT_400HZ[19].CLK
DipSwitch1 => comb~0.IN1
DipSwitch1 => BCD_TSEC[0].ENA
DipSwitch1 => BCD_TSEC[1].ENA
DipSwitch1 => BCD_TSEC[2].ENA
DipSwitch1 => BCD_TSEC[3].ENA
PBSwitch1 => PBSwitch1_flop1.DATAIN
PBSwitch2 => PBSwitch2_flop1.DATAIN
PBSwitch3 => PBSwitch3_flop1.DATAIN
LCD_RS <= LCD_RS~reg0.DB_MAX_OUTPUT_PORT_TYPE
LCD_E <= LCD_E~reg0.DB_MAX_OUTPUT_PORT_TYPE
RESET_LED <= reset.DB_MAX_OUTPUT_PORT_TYPE
SEC_LED <= BCD_SECD0[0].DB_MAX_OUTPUT_PORT_TYPE
ALARM_LED <= ALARM_LED~1.DB_MAX_OUTPUT_PORT_TYPE
LCD_RW <= LCD_RW~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATA_BUS[0] <= comb~1
DATA_BUS[1] <= comb~2
DATA_BUS[2] <= comb~3
DATA_BUS[3] <= comb~4
DATA_BUS[4] <= comb~5
DATA_BUS[5] <= comb~6
DATA_BUS[6] <= comb~7
DATA_BUS[7] <= comb~8