up3_clock.fit.qmsg

在UP3开发板上已经验证过的VHDL代码。 精确到十分之一秒

{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.574 ns register register " "Info: Estimated most critical path is register to register delay of 3.574 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BCD_SECD0\[0\] 1 REG LAB_X27_Y7 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X27_Y7; Fanout = 9; REG Node = 'BCD_SECD0\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BCD_SECD0[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 484 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.590 ns) 1.429 ns Selector9~226 2 COMB LAB_X27_Y9 1 " "Info: 2: + IC(0.839 ns) + CELL(0.590 ns) = 1.429 ns; Loc. = LAB_X27_Y9; Fanout = 1; COMB Node = 'Selector9~226'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.429 ns" { BCD_SECD0[0] Selector9~226 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.442 ns) 2.082 ns Selector9~227 3 COMB LAB_X27_Y9 1 " "Info: 3: + IC(0.211 ns) + CELL(0.442 ns) = 2.082 ns; Loc. = LAB_X27_Y9; Fanout = 1; COMB Node = 'Selector9~227'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Selector9~226 Selector9~227 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 2.735 ns Selector9~229 4 COMB LAB_X27_Y9 1 " "Info: 4: + IC(0.361 ns) + CELL(0.292 ns) = 2.735 ns; Loc. = LAB_X27_Y9; Fanout = 1; COMB Node = 'Selector9~229'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Selector9~227 Selector9~229 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.478 ns) 3.574 ns DATA_BUS_VALUE\[0\] 5 REG LAB_X27_Y9 2 " "Info: 5: + IC(0.361 ns) + CELL(0.478 ns) = 3.574 ns; Loc. = LAB_X27_Y9; Fanout = 2; REG Node = 'DATA_BUS_VALUE\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { Selector9~229 DATA_BUS_VALUE[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.802 ns ( 50.42 % ) " "Info: Total cell delay = 1.802 ns ( 50.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.772 ns ( 49.58 % ) " "Info: Total interconnect delay = 1.772 ns ( 49.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.574 ns" { BCD_SECD0[0] Selector9~226 Selector9~227 Selector9~229 DATA_BUS_VALUE[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 5 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 5%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x24_y0 x35_y10 " "Info: The peak interconnect region extends from location x24_y0 to location x35_y10" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Info: Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "8 " "Warning: Following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[0\] a permanently enabled " "Info: Pin DATA_BUS\[0\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[1\] a permanently enabled " "Info: Pin DATA_BUS\[1\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[2\] a permanently enabled " "Info: Pin DATA_BUS\[2\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[3\] a permanently enabled " "Info: Pin DATA_BUS\[3\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[4\] a permanently enabled " "Info: Pin DATA_BUS\[4\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[5\] a permanently enabled " "Info: Pin DATA_BUS\[5\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[6\] a permanently enabled " "Info: Pin DATA_BUS\[6\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[7\] a permanently enabled " "Info: Pin DATA_BUS\[7\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_RW GND " "Info: Pin LCD_RW has GND driving its datain port" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 12 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_RW } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_RW } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 28 15:35:45 2008 " "Info: Processing ended: Wed May 28 15:35:45 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.fit.smsg " "Info: Generated suppressed messages file C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}