up3_clock.tan.summary

在UP3开发板上已经验证过的VHDL代码。 精确到十分之一秒

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.432 ns
From           : DipSwitch2
To             : TEMP_BCD_HRD1[3]
From Clock     : --
To Clock       : CLK_48MHZ
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 25.063 ns
From           : BCD_HRD0[0]
To             : ALARM_LED
From Clock     : CLK_48MHZ
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 11.165 ns
From           : reset
To             : RESET_LED
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.838 ns
From           : DipSwitch1
To             : BCD_TSEC[0]
From Clock     : --
To Clock       : CLK_48MHZ
Failed Paths   : 0

Type           : Clock Setup: 'CLK_48MHZ'
Slack          : N/A
Required Time  : None
Actual Time    : 120.39 MHz ( period = 8.306 ns )
From           : BCD_SECD1[0]
To             : DATA_BUS_VALUE[0]
From Clock     : CLK_48MHZ
To Clock       : CLK_48MHZ
Failed Paths   : 0

Type           : Clock Hold: 'CLK_48MHZ'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : ALARM_BCD_HRD1[3]
To             : DATA_BUS_VALUE[3]
From Clock     : CLK_48MHZ
To Clock       : CLK_48MHZ
Failed Paths   : 9

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 9

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