📄 up3_clock.vwf

📁 在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒
💻 VWF
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字号:
	PARENT = "";
}

SIGNAL("SEC_LED")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("DATA_BUS[0]~result")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("DATA_BUS[1]~result")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("DATA_BUS[2]~result")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("DATA_BUS[3]~result")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("DATA_BUS[4]~result")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("DATA_BUS[5]~result")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("DATA_BUS[6]~result")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("DATA_BUS[7]~result")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("clk_48Mhz")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 48;
			LEVEL 0 FOR 10.4;
			LEVEL 1 FOR 10.4;
		}
		LEVEL 0 FOR 1.6;
	}
}

TRANSITION_LIST("reset")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10.4;
		LEVEL 1 FOR 989.6;
	}
}

TRANSITION_LIST("RESET_LED")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 10.4;
		LEVEL 0 FOR 989.6;
	}
}

TRANSITION_LIST("DATA_BUS[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 1000.0;
	}
}

TRANSITION_LIST("LCD_E")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("LCD_RS")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("LCD_RW")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_400HZ")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_10HZ")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_10HZ[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_10HZ[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_10HZ[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_10HZ[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_10HZ[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_10HZ[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_10HZ[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_10HZ[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[19]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[18]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[17]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[16]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 655.2;
		LEVEL 1 FOR 344.8;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 322.4;
		LEVEL 1 FOR 332.8;
		LEVEL 0 FOR 332.8;
		LEVEL 1 FOR 12.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 156.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 166.4;
			LEVEL 0 FOR 166.4;
		}
		LEVEL 1 FOR 166.4;
		LEVEL 0 FOR 12.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 72.8;
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 83.2;
			LEVEL 0 FOR 83.2;
		}
		LEVEL 1 FOR 83.2;
		LEVEL 0 FOR 12.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 31.2;
		NODE
		{
			REPEAT = 11;
			LEVEL 1 FOR 41.6;
			LEVEL 0 FOR 41.6;
		}
		LEVEL 1 FOR 41.6;
		LEVEL 0 FOR 12.0;
	}
}

TRANSITION_LIST("CLK_COUNT_400HZ[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10.4;
		NODE
		{
			REPEAT = 23;
			LEVEL 1 FOR 20.8;
			LEVEL 0 FOR 20.8;
		}
		LEVEL 1 FOR 20.8;
		LEVEL 0 FOR 12.0;
	}
}

TRANSITION_LIST("next_command")
{
	NODE
	{
		REPEAT = 1;
		LEVEL next_command.reset2 FOR 1000.0;
	}
}

TRANSITION_LIST("state")
{
	NODE
	{
		REPEAT = 1;
		LEVEL state.reset1 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_TSEC[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_TSEC[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_TSEC[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_TSEC[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_SECD0[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 52.0;
		LEVEL 1 FOR 948.0;
	}
}

TRANSITION_LIST("BCD_SECD0[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_SECD0[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 52.0;
		LEVEL 1 FOR 948.0;
	}
}

TRANSITION_LIST("BCD_SECD0[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 52.0;
		LEVEL 1 FOR 948.0;
	}
}

TRANSITION_LIST("BCD_SECD1[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_SECD1[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_SECD1[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_SECD1[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_MIND0[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_MIND0[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_MIND0[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_MIND0[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_MIND1[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_MIND1[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_MIND1[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_MIND1[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_HRD0[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_HRD0[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_HRD0[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_HRD0[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_HRD1[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_HRD1[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_HRD1[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("BCD_HRD1[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("PBSwitch1")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL 0 FOR 50.0;
			LEVEL 1 FOR 50.0;
		}
	}
}

TRANSITION_LIST("PBSwitch2")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("PBSwitch3")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("DipSwitch1")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("SEC_LED")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 52.0;
		LEVEL 1 FOR 948.0;
	}
}

TRANSITION_LIST("DATA_BUS[0]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[1]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[2]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[3]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[4]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[5]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[6]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("DATA_BUS[7]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk_48Mhz";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "reset";
	EXPAND_STATUS = COLLAPSED;
💿 文件大小 712 K
👤 上传用户 dan_che
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#VHDL #UP3 #开发板 #代码
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