📄 up3_clock.vhd
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next_command <= WRITE_CHAR21;
WHEN WRITE_CHAR21 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & ALARM_BCD_HRD1;
state <= TOGGLE_E;
next_command <= WRITE_CHAR22;
WHEN WRITE_CHAR22 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & ALARM_BCD_HRD0;
state <= TOGGLE_E;
next_command <= WRITE_CHAR23;
WHEN WRITE_CHAR23 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3A";
state <= TOGGLE_E;
next_command <= WRITE_CHAR24;
WHEN WRITE_CHAR24 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & ALARM_BCD_MIND1;
state <= TOGGLE_E;
next_command <= WRITE_CHAR25;
WHEN WRITE_CHAR25 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & ALARM_BCD_MIND0;
state <= TOGGLE_E;
next_command <= RETURN_HOME;
-- Return write address to first character postion
WHEN RETURN_HOME =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"80";
state <= TOGGLE_E;
next_command <= WRITE_CHART;
-- The next two states occur at the end of each command to the LCD
-- Toggle E line - falling edge loads inst/data to LCD controller
WHEN TOGGLE_E =>
LCD_E <= '0';
state <= HOLD;
-- Hold LCD inst/data valid after falling edge of E line
WHEN HOLD =>
state <= next_command;
END CASE;
END IF;
END PROCESS;
PROCESS (CLK_10HZ, reset)
BEGIN
IF reset = '0' THEN
BCD_HRD1 <= X"0";
BCD_HRD0 <= X"0";
BCD_MIND1 <= X"0";
BCD_MIND0 <= X"0";
BCD_SECD1 <= X"0";
BCD_SECD0 <= X"0";
BCD_TSEC <= X"0";
ELSIF( DipSwitch1 = '0' ) THEN
IF CLK_10HZ'EVENT AND CLK_10HZ = '1' THEN
-- TENTHS OF SECONDS
IF BCD_TSEC < 9 THEN
BCD_TSEC <= BCD_TSEC + 1;
ELSE
BCD_TSEC <= X"0";
-- SECONDS
IF BCD_SECD0 < 9 THEN
BCD_SECD0 <= BCD_SECD0 + 1;
ELSE
-- TENS OF SECONDS
BCD_SECD0 <= "0000";
IF BCD_SECD1 < 5 THEN
BCD_SECD1 <= BCD_SECD1 + 1;
ELSE
-- MINUTES
BCD_SECD1 <= "0000";
IF BCD_MIND0 < 9 THEN
BCD_MIND0 <= BCD_MIND0 + 1;
ELSE
-- TENS OF MINUTES
BCD_MIND0 <= "0000";
IF BCD_MIND1 < 5 THEN
BCD_MIND1 <= BCD_MIND1 + 1;
ELSE
-- HOURS
BCD_MIND1 <= "0000";
IF BCD_HRD0 < 9 AND NOT((BCD_HRD1 = 2) AND (BCD_HRD0 = 3))THEN
BCD_HRD0 <= BCD_HRD0 + 1;
ELSE
-- TENS OF HOURS
IF NOT((BCD_HRD1 = 2) AND (BCD_HRD0 = 3)) THEN
BCD_HRD1 <= BCD_HRD1 + 1;
BCD_HRD0 <= "0000";
ELSE
-- NEW DAY
BCD_HRD1 <= "0000";
BCD_HRD0 <= "0000";
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
ELSE
BCD_SECD0 <= TEMP_BCD_SECD0;
BCD_SECD1 <= TEMP_BCD_SECD1;
BCD_MIND0 <= TEMP_BCD_MIND0;
BCD_MIND1 <= TEMP_BCD_MIND1;
BCD_HRD0 <= TEMP_BCD_HRD0;
BCD_HRD1 <= TEMP_BCD_HRD1;
END IF;
END PROCESS;
count: PROCESS (CLK_48MHZ,PB1_valid,PB2_valid,PB3_valid)
BEGIN
IF rising_edge( CLK_48MHZ ) THEN
IF DipSwitch2 = '1' THEN
IF PB1_valid = '1' THEN
IF( TEMP_BCD_SECD0 < 9 ) THEN
TEMP_BCD_SECD0 <= TEMP_BCD_SECD0 + 1;
ELSIF( TEMP_BCD_SECD1 <5 ) THEN
TEMP_BCD_SECD0 <= "0000";
TEMP_BCD_SECD1 <= TEMP_BCD_SECD1 +1 ;
ELSE
TEMP_BCD_SECD0 <= "0000";
TEMP_BCD_SECD1 <= "0000";
END IF;
ELSIF PB2_valid = '1' THEN
IF( TEMP_BCD_MIND0 < 9 ) THEN
TEMP_BCD_MIND0 <= TEMP_BCD_MIND0 + 1;
ELSIF( TEMP_BCD_MIND1 <5 ) THEN
TEMP_BCD_MIND0 <= "0000";
TEMP_BCD_MIND1 <= TEMP_BCD_MIND1 + 1;
ELSE
TEMP_BCD_MIND0 <= "0000";
TEMP_BCD_MIND1 <= "0000";
END IF;
ELSIF PB3_valid = '1' THEN
IF( TEMP_BCD_HRD0 < 9 AND NOT((TEMP_BCD_HRD1 >= 2) AND (TEMP_BCD_HRD0 >= 3))) THEN
TEMP_BCD_HRD0 <= TEMP_BCD_HRD0 + 1;
ELSIF( NOT((TEMP_BCD_HRD1 >= 2) AND (TEMP_BCD_HRD0 >= 3))) THEN
TEMP_BCD_HRD0 <= "0000";
TEMP_BCD_HRD1 <= TEMP_BCD_HRD1 + 1;
ELSE
TEMP_BCD_HRD0 <= "0000";
TEMP_BCD_HRD1 <= "0000";
END IF;
END IF;
ELSE
IF PB2_valid = '1' THEN
IF( ALARM_BCD_MIND0 < 9 ) THEN
ALARM_BCD_MIND0 <= ALARM_BCD_MIND0 + 1;
ELSIF( ALARM_BCD_MIND1 <5 ) THEN
ALARM_BCD_MIND0 <= "0000";
ALARM_BCD_MIND1 <= ALARM_BCD_MIND1 + 1;
ELSE
ALARM_BCD_MIND0 <= "0000";
ALARM_BCD_MIND1 <= "0000";
END IF;
ELSIF PB3_valid = '1' THEN
IF( ALARM_BCD_HRD0 < 9 AND NOT((ALARM_BCD_HRD1 >= 2) AND (ALARM_BCD_HRD0 >= 3))) THEN
ALARM_BCD_HRD0 <= ALARM_BCD_HRD0 + 1;
ELSIF( NOT((ALARM_BCD_HRD1 >= 2) AND (ALARM_BCD_HRD0 >= 3))) THEN
ALARM_BCD_HRD0 <= "0000";
ALARM_BCD_HRD1 <= ALARM_BCD_HRD1 + 1;
ELSE
ALARM_BCD_HRD0 <= "0000";
ALARM_BCD_HRD1 <= "0000";
END IF;
END IF;
END IF;
END IF;
END PROCESS;
ALARM: PROCESS ( CLK_48MHZ )
BEGIN
IF ( BCD_MIND0 = 0 AND BCD_MIND1 =0) THEN
IF ( BCD_SECD0 < 4 AND BCD_SECD1 = 0 ) THEN
ALARM_LED <= '1';
ELSE ALARM_LED <= '0';
END IF;
ELSIF( ALARM_BCD_HRD1 = BCD_HRD1 AND ALARM_BCD_HRD0 = BCD_HRD0 AND ALARM_BCD_MIND1 = BCD_MIND1 AND ALARM_BCD_MIND0 = BCD_MIND0) THEN
IF ( BCD_SECD0 < 8 AND BCD_SECD1 = 0) THEN
ALARM_LED <= '1';
ELSE ALARM_LED <= '0';
END IF;
ELSE
ALARM_LED <= '0';
END IF;
END PROCESS;
---/////////////////////////////////////////////////////////////////////////////////////////////
---////////////////////////////////////////////////////////////////////////////////////////////
PB1_flop: process (CLK_48MHZ, reset)
begin
if reset = '0' then
PBSwitch1_flop1 <= '1';
PBSwitch1_flop2 <= '1';
elsif rising_edge (CLK_48MHZ) then
PBSwitch1_flop1 <= PBSwitch1;
PBSwitch1_flop2 <= PBSwitch1_flop1;
end if;
end process;
--********************************************************************************************
-- This process module generates stable pulse
--********************************************************************************************
PB1_pulse: process (PBSwitch1, PBSwitch1_flop1, PBSwitch1_flop2)
begin
PB1_PulseOut <= PBSwitch1_flop2 and (not PBSwitch1_flop1);
end process;
--********************************************************************************************
-- Debounce Logic
--********************************************************************************************
PB1_debounce: process (CLK_48MHZ, reset)
begin
if reset = '0' then
count1 <= (others => '0');
elsif rising_edge (CLK_48MHZ) then
if (PBSwitch1_flop1 = '0') then
if (PB1_PulseOut = '1') then
count1 <= debounce_count;
else
if (count1 = mincount) then
count1 <= (others => '0');
else
count1 <= count1 - 1;
end if;
end if;
else
count1 <= (others => '0');
end if;
end if;
end process;
PB1_out: process (count1)
begin
case count1 is
when "0000000000000001" => if (PB1_PulseOut = '0') then
PB1_valid <= '1';
else
PB1_valid <= '0';
end if;
when others => PB1_valid <= '0';
end case;
end process;
---/////////////////////////////////////////////////////////////////////////////////////////////
---////////////////////////////////////////////////////////////////////////////////////////////
PB2_flop: process (CLK_48MHZ, reset)
begin
if reset = '0' then
PBSwitch2_flop1 <= '1';
PBSwitch2_flop2 <= '1';
elsif rising_edge (CLK_48MHZ) then
PBSwitch2_flop1 <= PBSwitch2;
PBSwitch2_flop2 <= PBSwitch2_flop1;
end if;
end process;
--********************************************************************************************
-- This process module generates stable pulse
--********************************************************************************************
PB2_pulse: process (PBSwitch2, PBSwitch2_flop1, PBSwitch2_flop2)
begin
PB2_PulseOut <= PBSwitch2_flop2 and (not PBSwitch2_flop1);
end process;
--********************************************************************************************
-- Debounce Logic
--********************************************************************************************
PB2_debounce: process (CLK_48MHZ, reset)
begin
if reset = '0' then
count2 <= (others => '0');
elsif rising_edge (CLK_48MHZ) then
if (PBSwitch2_flop1 = '0') then
if (PB2_PulseOut = '1') then
count2 <= debounce_count;
else
if (count2 = mincount) then
count2 <= (others => '0');
else
count2 <= count2 - 1;
end if;
end if;
else
count2 <= (others => '0');
end if;
end if;
end process;
PB2_out: process (count2)
begin
case count2 is
when "0000000000000001" => if (PB2_PulseOut = '0') then
PB2_valid <= '1';
else
PB2_valid <= '0';
end if;
when others => PB2_valid <= '0';
end case;
end process;
---/////////////////////////////////////////////////////////////////////////////////////////////
---////////////////////////////////////////////////////////////////////////////////////////////
PB3_flop: process (CLK_48MHZ, reset)
begin
if reset = '0' then
PBSwitch3_flop1 <= '1';
PBSwitch3_flop2 <= '1';
elsif rising_edge (CLK_48MHZ) then
PBSwitch3_flop1 <= PBSwitch3;
PBSwitch3_flop2 <= PBSwitch3_flop1;
end if;
end process;
--********************************************************************************************
-- This process module generates stable pulse
--********************************************************************************************
PB3_pulse: process (PBSwitch3, PBSwitch3_flop1, PBSwitch3_flop2)
begin
PB3_PulseOut <= PBSwitch3_flop2 and (not PBSwitch3_flop1);
end process;
--********************************************************************************************
-- Debounce Logic
--********************************************************************************************
PB3_debounce: process (CLK_48MHZ, reset)
begin
if reset = '0' then
count3 <= (others => '0');
elsif rising_edge (CLK_48MHZ) then
if (PBSwitch3_flop1 = '0') then
if (PB3_PulseOut = '1') then
count3 <= debounce_count;
else
if (count3 = mincount) then
count3 <= (others => '0');
else
count3 <= count3 - 1;
end if;
end if;
else
count3 <= (others => '0');
end if;
end if;
end process;
PB3_out: process (count3)
begin
case count3 is
when "0000000000000001" => if (PB3_PulseOut = '0') then
PB3_valid <= '1';
else
PB3_valid <= '0';
end if;
when others => PB3_valid <= '0';
end case;
end process;
---///////////////////////////////////////////////////////////////////////////////////
END a;
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