seg.vhd

自己做的开发板

--
------------------------------------------------------------------------------------
-- DESCRIPTION   :   BIN to seven segments converter
--                   segment encoding
--                        a
--                      +---+ 
--                    f |   | b
--                      +---+  <- g
--                    e |   | c
--                      +---+
--                        d
--                  Enable (EN) active                : high
--                  Outputs (data_out) active         : low
-- Download from :  http://www.pld.com.cn
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;

entity seg is port 
	(
		clock:in std_logic;
		pin5: out std_logic_vector (11 downto 0);
		data_clk: out std_logic_vector (7 downto 0);
		data_out: out std_logic_vector (7 downto 0)
	);
end entity;



architecture bin27seg_arch of seg is
signal Num:Integer range 0 to 2000000 ;
signal cnt4: Integer range 0 to 17;
signal clk: std_logic_vector (7 downto 0);
signal seg_out: STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
  PROCESS(clock)
	BEGIN
	if rising_edge(clock) then
		if clk = "00000000" then
			clk <= "11111111";
		end if;
		if Num = 2000000 then
			Num <= 0;
			cnt4 <= cnt4 + 1;
			if cnt4 > 16 then
				cnt4 <= 0;
				Num <= 1999999;
			else
				case cnt4 is
					when 0 =>seg_out<= "01000000";
					when 1 =>seg_out<= "11111001";
					when 2 =>seg_out<= "00100100";
					when 3 =>seg_out<= "00110000";
					when 4 =>seg_out<= "00011001";
					when 5 =>seg_out<= "00010010";
					when 6 =>seg_out<= "00000010";
					when 7 =>seg_out<= "01111000";
					when 8 =>seg_out<= "00000000";
					when 9 =>seg_out<= "00010000";
					when 10 =>seg_out<= "00001000";
					when 11 =>seg_out<= "00000011";
					when 12 =>seg_out<= "01000110";
					when 13 =>seg_out<= "00100001";
					when 14 =>seg_out<= "00000110";
					when 15 =>seg_out<= "00001110";
					when others=>seg_out<= "11111111";
				end case;
			end if;
		else
			Num <= Num + 1;
		end if;
	end if;
  END PROCESS;
	pin5 <= "000000000000";
	data_clk <= clk;
	data_out <= seg_out;
end;