seg.map.qmsg

自己做的开发板

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 23 09:59:11 2008 " "Info: Processing started: Fri May 23 09:59:11 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off seg -c seg " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off seg -c seg" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg-bin27seg_arch " "Info: Found design unit 1: seg-bin27seg_arch" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 33 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 seg " "Info: Found entity 1: seg" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 22 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "clk\[7\] High " "Info: Power-up level of register \"clk\[7\]\" is not specified -- using power-up level of High to minimize register" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clk\[7\] data_in VCC " "Warning: Reduced register \"clk\[7\]\" with stuck data_in port to stuck value VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "clk\[6\] High " "Info: Power-up level of register \"clk\[6\]\" is not specified -- using power-up level of High to minimize register" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clk\[6\] data_in VCC " "Warning: Reduced register \"clk\[6\]\" with stuck data_in port to stuck value VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "clk\[5\] High " "Info: Power-up level of register \"clk\[5\]\" is not specified -- using power-up level of High to minimize register" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clk\[5\] data_in VCC " "Warning: Reduced register \"clk\[5\]\" with stuck data_in port to stuck value VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "clk\[4\] High " "Info: Power-up level of register \"clk\[4\]\" is not specified -- using power-up level of High to minimize register" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clk\[4\] data_in VCC " "Warning: Reduced register \"clk\[4\]\" with stuck data_in port to stuck value VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "clk\[3\] High " "Info: Power-up level of register \"clk\[3\]\" is not specified -- using power-up level of High to minimize register" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clk\[3\] data_in VCC " "Warning: Reduced register \"clk\[3\]\" with stuck data_in port to stuck value VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "clk\[2\] High " "Info: Power-up level of register \"clk\[2\]\" is not specified -- using power-up level of High to minimize register" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clk\[2\] data_in VCC " "Warning: Reduced register \"clk\[2\]\" with stuck data_in port to stuck value VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "clk\[1\] High " "Info: Power-up level of register \"clk\[1\]\" is not specified -- using power-up level of High to minimize register" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clk\[1\] data_in VCC " "Warning: Reduced register \"clk\[1\]\" with stuck data_in port to stuck value VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "clk\[0\] High " "Info: Power-up level of register \"clk\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clk\[0\] data_in VCC " "Warning: Reduced register \"clk\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt4\[0\]~10 5 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: \"cnt4\[0\]~10\"" {  } { { "seg.vhd" "cnt4\[0\]~10" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "21 " "Info: Ignored 21 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "21 " "Info: Ignored 21 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "pin5\[11\] GND " "Warning: Pin \"pin5\[11\]\" stuck at GND" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pin5\[10\] GND " "Warning: Pin \"pin5\[10\]\" stuck at GND" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pin5\[9\] GND " "Warning: Pin \"pin5\[9\]\" stuck at GND" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pin5\[8\] GND " "Warning: Pin \"pin5\[8\]\" stuck at GND" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pin5\[7\] GND " "Warning: Pin \"pin5\[7\]\" stuck at GND" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pin5\[6\] GND " "Warning: Pin \"pin5\[6\]\" stuck at GND" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pin5\[5\] GND " "Warning: Pin \"pin5\[5\]\" stuck at GND" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pin5\[4\] GND " "Warning: Pin \"pin5\[4\]\" stuck at GND" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pin5\[3\] GND " "Warning: Pin \"pin5\[3\]\" stuck at GND" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pin5\[2\] GND " "Warning: Pin \"pin5\[2\]\" stuck at GND" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pin5\[1\] GND " "Warning: Pin \"pin5\[1\]\" stuck at GND" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pin5\[0\] GND " "Warning: Pin \"pin5\[0\]\" stuck at GND" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "data_clk\[7\] VCC " "Warning: Pin \"data_clk\[7\]\" stuck at VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 26 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "data_clk\[6\] VCC " "Warning: Pin \"data_clk\[6\]\" stuck at VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 26 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "data_clk\[5\] VCC " "Warning: Pin \"data_clk\[5\]\" stuck at VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 26 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "data_clk\[4\] VCC " "Warning: Pin \"data_clk\[4\]\" stuck at VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 26 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "data_clk\[3\] VCC " "Warning: Pin \"data_clk\[3\]\" stuck at VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 26 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "data_clk\[2\] VCC " "Warning: Pin \"data_clk\[2\]\" stuck at VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 26 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "data_clk\[1\] VCC " "Warning: Pin \"data_clk\[1\]\" stuck at VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 26 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "data_clk\[0\] VCC " "Warning: Pin \"data_clk\[0\]\" stuck at VCC" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 26 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock " "Info: Promoted clock signal driven by pin \"clock\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock " "Info: Promoted clock signal driven by pin \"clock\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "109 " "Info: Implemented 109 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "28 " "Info: Implemented 28 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "54 " "Info: Implemented 54 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "26 " "Info: Implemented 26 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 29 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 29 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 23 09:59:19 2008 " "Info: Processing ended: Fri May 23 09:59:19 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}