seg.tan.qmsg

自己做的开发板

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 24 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register lpm_counter:cnt4_rtl_0\|dffs\[0\] register Num\[20\] 66.67 MHz 15.0 ns Internal " "Info: Clock \"clock\" has Internal fmax of 66.67 MHz between source register \"lpm_counter:cnt4_rtl_0\|dffs\[0\]\" and destination register \"Num\[20\]\" (period= 15.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.000 ns + Longest register register " "Info: + Longest register to register delay is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt4_rtl_0\|dffs\[0\] 1 REG LC13 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC13; Fanout = 33; REG Node = 'lpm_counter:cnt4_rtl_0\|dffs\[0\]'" {  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "" { lpm_counter:cnt4_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns Num~530 2 COMB SEXP17 6 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = SEXP17; Fanout = 6; COMB Node = 'Num~530'" {  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "6.000 ns" { lpm_counter:cnt4_rtl_0|dffs[0] Num~530 } "NODE_NAME" } "" } } { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 11.000 ns Num\[20\] 3 REG LC22 36 " "Info: 3: + IC(0.000 ns) + CELL(5.000 ns) = 11.000 ns; Loc. = LC22; Fanout = 36; REG Node = 'Num\[20\]'" {  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "5.000 ns" { Num~530 Num[20] } "NODE_NAME" } "" } } { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 90.91 % " "Info: Total cell delay = 10.000 ns ( 90.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 9.09 % " "Info: Total interconnect delay = 1.000 ns ( 9.09 % )" {  } {  } 0}  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "11.000 ns" { lpm_counter:cnt4_rtl_0|dffs[0] Num~530 Num[20] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "11.000 ns" { lpm_counter:cnt4_rtl_0|dffs[0] Num~530 Num[20] } { 0.000ns 1.000ns 0.000ns } { 0.000ns 5.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clock 1 CLK PIN_43 34 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_43; Fanout = 34; CLK Node = 'clock'" {  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "" { clock } "NODE_NAME" } "" } } { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns Num\[20\] 2 REG LC22 36 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC22; Fanout = 36; REG Node = 'Num\[20\]'" {  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "0.000 ns" { clock Num[20] } "NODE_NAME" } "" } } { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "1.500 ns" { clock Num[20] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { clock clock~out Num[20] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clock 1 CLK PIN_43 34 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_43; Fanout = 34; CLK Node = 'clock'" {  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "" { clock } "NODE_NAME" } "" } } { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns lpm_counter:cnt4_rtl_0\|dffs\[0\] 2 REG LC13 33 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC13; Fanout = 33; REG Node = 'lpm_counter:cnt4_rtl_0\|dffs\[0\]'" {  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "0.000 ns" { clock lpm_counter:cnt4_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "1.500 ns" { clock lpm_counter:cnt4_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { clock clock~out lpm_counter:cnt4_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "1.500 ns" { clock Num[20] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { clock clock~out Num[20] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "1.500 ns" { clock lpm_counter:cnt4_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { clock clock~out lpm_counter:cnt4_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0}  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "11.000 ns" { lpm_counter:cnt4_rtl_0|dffs[0] Num~530 Num[20] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "11.000 ns" { lpm_counter:cnt4_rtl_0|dffs[0] Num~530 Num[20] } { 0.000ns 1.000ns 0.000ns } { 0.000ns 5.000ns 5.000ns } } } { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "1.500 ns" { clock Num[20] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { clock clock~out Num[20] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "1.500 ns" { clock lpm_counter:cnt4_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { clock clock~out lpm_counter:cnt4_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock data_out\[0\] seg_out\[0\] 5.000 ns register " "Info: tco from clock \"clock\" to destination pin \"data_out\[0\]\" through register \"seg_out\[0\]\" is 5.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clock 1 CLK PIN_43 34 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_43; Fanout = 34; CLK Node = 'clock'" {  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "" { clock } "NODE_NAME" } "" } } { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns seg_out\[0\] 2 REG LC64 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC64; Fanout = 1; REG Node = 'seg_out\[0\]'" {  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "0.000 ns" { clock seg_out[0] } "NODE_NAME" } "" } } { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "1.500 ns" { clock seg_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { clock clock~out seg_out[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register pin " "Info: + Longest register to pin delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seg_out\[0\] 1 REG LC64 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC64; Fanout = 1; REG Node = 'seg_out\[0\]'" {  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "" { seg_out[0] } "NODE_NAME" } "" } } { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns data_out\[0\] 2 PIN PIN_41 0 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'data_out\[0\]'" {  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "1.500 ns" { seg_out[0] data_out[0] } "NODE_NAME" } "" } } { "seg.vhd" "" { Text "E:/CPLD/seg/seg.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "1.500 ns" { seg_out[0] data_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { seg_out[0] data_out[0] } { 0.000ns 0.000ns } { 0.000ns 1.500ns } } }  } 0}  } { { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "1.500 ns" { clock seg_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { clock clock~out seg_out[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "E:/CPLD/seg/db/seg_cmp.qrpt" "" { Report "E:/CPLD/seg/db/seg_cmp.qrpt" Compiler "seg" "UNKNOWN" "V1" "E:/CPLD/seg/db/seg.quartus_db" { Floorplan "E:/CPLD/seg/" "" "1.500 ns" { seg_out[0] data_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { seg_out[0] data_out[0] } { 0.000ns 0.000ns } { 0.000ns 1.500ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 23 09:59:25 2008 " "Info: Processing ended: Fri May 23 09:59:25 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}