seg.tan.rpt

自己做的开发板

; N/A                                     ; 66.67 MHz ( period = 15.000 ns )                    ; Num[13]                        ; Num[10] ; clock      ; clock    ; None                        ; None                      ; 11.000 ns               ;
; N/A                                     ; 66.67 MHz ( period = 15.000 ns )                    ; Num[19]                        ; Num[10] ; clock      ; clock    ; None                        ; None                      ; 11.000 ns               ;
; N/A                                     ; 66.67 MHz ( period = 15.000 ns )                    ; Num[18]                        ; Num[10] ; clock      ; clock    ; None                        ; None                      ; 11.000 ns               ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                ;         ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+------------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To          ; From Clock ;
+-------+--------------+------------+------------+-------------+------------+
; N/A   ; None         ; 5.000 ns   ; seg_out[0] ; data_out[0] ; clock      ;
; N/A   ; None         ; 5.000 ns   ; seg_out[3] ; data_out[3] ; clock      ;
; N/A   ; None         ; 5.000 ns   ; seg_out[1] ; data_out[1] ; clock      ;
; N/A   ; None         ; 5.000 ns   ; seg_out[2] ; data_out[2] ; clock      ;
; N/A   ; None         ; 5.000 ns   ; seg_out[4] ; data_out[4] ; clock      ;
; N/A   ; None         ; 5.000 ns   ; seg_out[5] ; data_out[5] ; clock      ;
; N/A   ; None         ; 5.000 ns   ; seg_out[6] ; data_out[6] ; clock      ;
; N/A   ; None         ; 5.000 ns   ; seg_out[7] ; data_out[7] ; clock      ;
+-------+--------------+------------+------------+-------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Fri May 23 09:59:24 2008
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off seg -c seg
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 66.67 MHz between source register "lpm_counter:cnt4_rtl_0|dffs[0]" and destination register "Num[20]" (period= 15.0 ns)
    Info: + Longest register to register delay is 11.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC13; Fanout = 33; REG Node = 'lpm_counter:cnt4_rtl_0|dffs[0]'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = SEXP17; Fanout = 6; COMB Node = 'Num~530'
        Info: 3: + IC(0.000 ns) + CELL(5.000 ns) = 11.000 ns; Loc. = LC22; Fanout = 36; REG Node = 'Num[20]'
        Info: Total cell delay = 10.000 ns ( 90.91 % )
        Info: Total interconnect delay = 1.000 ns ( 9.09 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock" to destination register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_43; Fanout = 34; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC22; Fanout = 36; REG Node = 'Num[20]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
        Info: - Longest clock path from clock "clock" to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_43; Fanout = 34; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC13; Fanout = 33; REG Node = 'lpm_counter:cnt4_rtl_0|dffs[0]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Micro setup delay of destination is 2.000 ns
Info: tco from clock "clock" to destination pin "data_out[0]" through register "seg_out[0]" is 5.000 ns
    Info: + Longest clock path from clock "clock" to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_43; Fanout = 34; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC64; Fanout = 1; REG Node = 'seg_out[0]'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Longest register to pin delay is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC64; Fanout = 1; REG Node = 'seg_out[0]'
        Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'data_out[0]'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri May 23 09:59:25 2008
    Info: Elapsed time: 00:00:01