seg.qsf

自己做的开发板

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		seg_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:22:07  MAY 07, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 4.2
set_global_assignment -name VHDL_FILE seg.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE seg.vwf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_43 -to clock
set_location_assignment PIN_41 -to data_out[0]
set_location_assignment PIN_40 -to data_out[1]
set_location_assignment PIN_39 -to data_out[2]
set_location_assignment PIN_4 -to data_out[3]
set_location_assignment PIN_25 -to data_clk[0]
set_location_assignment PIN_24 -to data_clk[1]
set_location_assignment PIN_21 -to data_clk[2]
set_location_assignment PIN_20 -to data_clk[3]
set_location_assignment PIN_37 -to data_out[4]
set_location_assignment PIN_36 -to data_out[5]
set_location_assignment PIN_34 -to data_out[6]
set_location_assignment PIN_5 -to pin5[0]
set_location_assignment PIN_6 -to pin5[1]
set_location_assignment PIN_8 -to pin5[2]
set_location_assignment PIN_9 -to pin5[3]
set_location_assignment PIN_11 -to pin5[4]
set_location_assignment PIN_12 -to pin5[5]
set_location_assignment PIN_14 -to pin5[6]
set_location_assignment PIN_26 -to pin5[7]
set_location_assignment PIN_28 -to pin5[8]
set_location_assignment PIN_31 -to pin5[10]
set_location_assignment PIN_27 -to pin5[11]
set_location_assignment PIN_29 -to pin5[9]
set_location_assignment PIN_19 -to data_clk[4]
set_location_assignment PIN_17 -to data_clk[6]
set_location_assignment PIN_16 -to data_clk[7]
set_location_assignment PIN_33 -to data_out[7]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 44
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 10
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name TOP_LEVEL_ENTITY seg

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPM7064SLC44-10"

# Simulator Assignments
# =====================
set_global_assignment -name GLITCH_INTERVAL "1 "