pll2.hier_info

PLL 时钟模块 Quartus II平台的简单设计实例 附仿真波形

|PLL2
areset => areset~0.IN1
inclk0 => sub_wire13[0].IN1
scanaclr => scanaclr~0.IN1
scanclk => scanclk~0.IN1
scandata => scandata~0.IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk
c2 <= altpll:altpll_component.clk
e0 <= altpll:altpll_component.extclk
e1 <= altpll:altpll_component.extclk
locked <= altpll:altpll_component.locked
scandataout <= altpll:altpll_component.scandataout


|PLL2|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => pll.ARESET
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => pll.SCANCLK
scanaclr => pll.SCANACLR
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => pll.SCANDATA
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= pll.CLK2
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= pll.EXTCLK
extclk[1] <= pll.EXTCLK1
extclk[2] <= <UNC>
extclk[3] <= <UNC>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= pll.LOCKED
scandataout <= pll.SCANDATAOUT
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE