pll2.tan.qmsg

PLL 时钟模块 Quartus II平台的简单设计实例 附仿真波形

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "scanclk register altpll:altpll_component\|_scandataout register altpll:altpll_component\|_scandataout 25.0 MHz 40.0 ns Internal " "Info: Clock \"scanclk\" has Internal fmax of 25.0 MHz between source register \"altpll:altpll_component\|_scandataout\" and destination register \"altpll:altpll_component\|_scandataout\" (period= 40.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "39.890 ns + Longest register register " "Info: + Longest register to register delay is 39.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll:altpll_component\|_scandataout 1 REG PLL_5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 2; REG Node = 'altpll:altpll_component\|_scandataout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_scandataout } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(39.890 ns) 39.890 ns altpll:altpll_component\|_scandataout 2 REG PLL_5 2 " "Info: 2: + IC(0.000 ns) + CELL(39.890 ns) = 39.890 ns; Loc. = PLL_5; Fanout = 2; REG Node = 'altpll:altpll_component\|_scandataout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "39.890 ns" { altpll:altpll_component|_scandataout altpll:altpll_component|_scandataout } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "39.890 ns ( 100.00 % ) " "Info: Total cell delay = 39.890 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "39.890 ns" { altpll:altpll_component|_scandataout altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "39.890 ns" { altpll:altpll_component|_scandataout altpll:altpll_component|_scandataout } { 0.000ns 0.000ns } { 0.000ns 39.890ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "scanclk destination 4.965 ns + Shortest register " "Info: + Shortest clock path from clock \"scanclk\" to destination register is 4.965 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns scanclk 1 CLK PIN_C12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_C12; Fanout = 1; CLK Node = 'scanclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scanclk } "NODE_NAME" } } { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.824 ns) + CELL(2.000 ns) 4.965 ns altpll:altpll_component\|_scandataout 2 REG PLL_5 2 " "Info: 2: + IC(1.824 ns) + CELL(2.000 ns) = 4.965 ns; Loc. = PLL_5; Fanout = 2; REG Node = 'altpll:altpll_component\|_scandataout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.824 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.141 ns ( 63.26 % ) " "Info: Total cell delay = 3.141 ns ( 63.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.824 ns ( 36.74 % ) " "Info: Total interconnect delay = 1.824 ns ( 36.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.965 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.965 ns" { scanclk scanclk~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 1.824ns } { 0.000ns 1.141ns 2.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "scanclk source 4.965 ns - Longest register " "Info: - Longest clock path from clock \"scanclk\" to source register is 4.965 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns scanclk 1 CLK PIN_C12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_C12; Fanout = 1; CLK Node = 'scanclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scanclk } "NODE_NAME" } } { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.824 ns) + CELL(2.000 ns) 4.965 ns altpll:altpll_component\|_scandataout 2 REG PLL_5 2 " "Info: 2: + IC(1.824 ns) + CELL(2.000 ns) = 4.965 ns; Loc. = PLL_5; Fanout = 2; REG Node = 'altpll:altpll_component\|_scandataout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.824 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.141 ns ( 63.26 % ) " "Info: Total cell delay = 3.141 ns ( 63.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.824 ns ( 36.74 % ) " "Info: Total interconnect delay = 1.824 ns ( 36.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.965 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.965 ns" { scanclk scanclk~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 1.824ns } { 0.000ns 1.141ns 2.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.965 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.965 ns" { scanclk scanclk~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 1.824ns } { 0.000ns 1.141ns 2.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.965 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.965 ns" { scanclk scanclk~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 1.824ns } { 0.000ns 1.141ns 2.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.100 ns + " "Info: + Micro clock to output delay of source is 0.100 ns" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "39.890 ns" { altpll:altpll_component|_scandataout altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "39.890 ns" { altpll:altpll_component|_scandataout altpll:altpll_component|_scandataout } { 0.000ns 0.000ns } { 0.000ns 39.890ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.965 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.965 ns" { scanclk scanclk~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 1.824ns } { 0.000ns 1.141ns 2.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.965 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.965 ns" { scanclk scanclk~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 1.824ns } { 0.000ns 1.141ns 2.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "altpll:altpll_component\|_scandataout scandata scanclk 2.737 ns register " "Info: tsu for register \"altpll:altpll_component\|_scandataout\" (data pin = \"scandata\", clock pin = \"scanclk\") is 2.737 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.692 ns + Longest pin register " "Info: + Longest pin to register delay is 7.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns scandata 1 PIN PIN_F12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_F12; Fanout = 1; PIN Node = 'scandata'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scandata } "NODE_NAME" } } { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.551 ns) + CELL(2.000 ns) 7.692 ns altpll:altpll_component\|_scandataout 2 REG PLL_5 2 " "Info: 2: + IC(4.551 ns) + CELL(2.000 ns) = 7.692 ns; Loc. = PLL_5; Fanout = 2; REG Node = 'altpll:altpll_component\|_scandataout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.551 ns" { scandata altpll:altpll_component|_scandataout } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.141 ns ( 40.83 % ) " "Info: Total cell delay = 3.141 ns ( 40.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.551 ns ( 59.17 % ) " "Info: Total interconnect delay = 4.551 ns ( 59.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.692 ns" { scandata altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.692 ns" { scandata scandata~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 4.551ns } { 0.000ns 1.141ns 2.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "scanclk destination 4.965 ns - Shortest register " "Info: - Shortest clock path from clock \"scanclk\" to destination register is 4.965 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns scanclk 1 CLK PIN_C12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_C12; Fanout = 1; CLK Node = 'scanclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scanclk } "NODE_NAME" } } { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.824 ns) + CELL(2.000 ns) 4.965 ns altpll:altpll_component\|_scandataout 2 REG PLL_5 2 " "Info: 2: + IC(1.824 ns) + CELL(2.000 ns) = 4.965 ns; Loc. = PLL_5; Fanout = 2; REG Node = 'altpll:altpll_component\|_scandataout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.824 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.141 ns ( 63.26 % ) " "Info: Total cell delay = 3.141 ns ( 63.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.824 ns ( 36.74 % ) " "Info: Total interconnect delay = 1.824 ns ( 36.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.965 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.965 ns" { scanclk scanclk~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 1.824ns } { 0.000ns 1.141ns 2.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.692 ns" { scandata altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.692 ns" { scandata scandata~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 4.551ns } { 0.000ns 1.141ns 2.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.965 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.965 ns" { scanclk scanclk~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 1.824ns } { 0.000ns 1.141ns 2.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "scanclk scandataout altpll:altpll_component\|_scandataout 9.553 ns register " "Info: tco from clock \"scanclk\" to destination pin \"scandataout\" through register \"altpll:altpll_component\|_scandataout\" is 9.553 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "scanclk source 4.965 ns + Longest register " "Info: + Longest clock path from clock \"scanclk\" to source register is 4.965 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns scanclk 1 CLK PIN_C12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_C12; Fanout = 1; CLK Node = 'scanclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scanclk } "NODE_NAME" } } { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.824 ns) + CELL(2.000 ns) 4.965 ns altpll:altpll_component\|_scandataout 2 REG PLL_5 2 " "Info: 2: + IC(1.824 ns) + CELL(2.000 ns) = 4.965 ns; Loc. = PLL_5; Fanout = 2; REG Node = 'altpll:altpll_component\|_scandataout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.824 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.141 ns ( 63.26 % ) " "Info: Total cell delay = 3.141 ns ( 63.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.824 ns ( 36.74 % ) " "Info: Total interconnect delay = 1.824 ns ( 36.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.965 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.965 ns" { scanclk scanclk~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 1.824ns } { 0.000ns 1.141ns 2.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.100 ns + " "Info: + Micro clock to output delay of source is 0.100 ns" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.488 ns + Longest register pin " "Info: + Longest register to pin delay is 4.488 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll:altpll_component\|_scandataout 1 REG PLL_5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 2; REG Node = 'altpll:altpll_component\|_scandataout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_scandataout } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.984 ns) + CELL(2.504 ns) 4.488 ns scandataout 2 PIN PIN_F15 0 " "Info: 2: + IC(1.984 ns) + CELL(2.504 ns) = 4.488 ns; Loc. = PIN_F15; Fanout = 0; PIN Node = 'scandataout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.488 ns" { altpll:altpll_component|_scandataout scandataout } "NODE_NAME" } } { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.504 ns ( 55.79 % ) " "Info: Total cell delay = 2.504 ns ( 55.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.984 ns ( 44.21 % ) " "Info: Total interconnect delay = 1.984 ns ( 44.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.488 ns" { altpll:altpll_component|_scandataout scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.488 ns" { altpll:altpll_component|_scandataout scandataout } { 0.000ns 1.984ns } { 0.000ns 2.504ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.965 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.965 ns" { scanclk scanclk~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 1.824ns } { 0.000ns 1.141ns 2.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.488 ns" { altpll:altpll_component|_scandataout scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.488 ns" { altpll:altpll_component|_scandataout scandataout } { 0.000ns 1.984ns } { 0.000ns 2.504ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "altpll:altpll_component\|_scandataout scandata scanclk -2.677 ns register " "Info: th for register \"altpll:altpll_component\|_scandataout\" (data pin = \"scandata\", clock pin = \"scanclk\") is -2.677 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "scanclk destination 4.965 ns + Longest register " "Info: + Longest clock path from clock \"scanclk\" to destination register is 4.965 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns scanclk 1 CLK PIN_C12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_C12; Fanout = 1; CLK Node = 'scanclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scanclk } "NODE_NAME" } } { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.824 ns) + CELL(2.000 ns) 4.965 ns altpll:altpll_component\|_scandataout 2 REG PLL_5 2 " "Info: 2: + IC(1.824 ns) + CELL(2.000 ns) = 4.965 ns; Loc. = PLL_5; Fanout = 2; REG Node = 'altpll:altpll_component\|_scandataout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.824 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.141 ns ( 63.26 % ) " "Info: Total cell delay = 3.141 ns ( 63.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.824 ns ( 36.74 % ) " "Info: Total interconnect delay = 1.824 ns ( 36.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.965 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.965 ns" { scanclk scanclk~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 1.824ns } { 0.000ns 1.141ns 2.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.050 ns + " "Info: + Micro hold delay of destination is 0.050 ns" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.692 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns scandata 1 PIN PIN_F12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_F12; Fanout = 1; PIN Node = 'scandata'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scandata } "NODE_NAME" } } { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.551 ns) + CELL(2.000 ns) 7.692 ns altpll:altpll_component\|_scandataout 2 REG PLL_5 2 " "Info: 2: + IC(4.551 ns) + CELL(2.000 ns) = 7.692 ns; Loc. = PLL_5; Fanout = 2; REG Node = 'altpll:altpll_component\|_scandataout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.551 ns" { scandata altpll:altpll_component|_scandataout } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 797 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.141 ns ( 40.83 % ) " "Info: Total cell delay = 3.141 ns ( 40.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.551 ns ( 59.17 % ) " "Info: Total interconnect delay = 4.551 ns ( 59.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.692 ns" { scandata altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.692 ns" { scandata scandata~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 4.551ns } { 0.000ns 1.141ns 2.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.965 ns" { scanclk altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.965 ns" { scanclk scanclk~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 1.824ns } { 0.000ns 1.141ns 2.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.692 ns" { scandata altpll:altpll_component|_scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.692 ns" { scandata scandata~out0 altpll:altpll_component|_scandataout } { 0.000ns 0.000ns 4.551ns } { 0.000ns 1.141ns 2.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 25 10:17:20 2008 " "Info: Processing ended: Sun May 25 10:17:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}