📄 pll2.tan.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 25 10:17:19 2008 " "Info: Processing started: Sun May 25 10:17:19 2008" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off PLL2 -c PLL2 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PLL2 -c PLL2 --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" { } { } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "scanclk " "Info: Assuming node \"scanclk\" is an undefined clock" { } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 53 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "scanclk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 0 0}
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