ledwalk.tan.rpt

Verylog编写的 Quartus II平台的简单设计实例 附仿真波形

; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[1]  ; LFEG[1]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[3]  ; LFEG[1]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[4]  ; LFEG[1]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[5]  ; LFEG[1]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[6]  ; LFEG[1]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[7]  ; LFEG[1]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[8]  ; LFEG[1]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[9]  ; LFEG[1]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[10] ; LFEG[1]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[11] ; LFEG[1]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[2]  ; LFEG[3]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[3]  ; LFEG[4]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[4]  ; LFEG[5]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[5]  ; LFEG[6]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[6]  ; LFEG[7]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[7]  ; LFEG[8]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[8]  ; LFEG[9]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[9]  ; LFEG[10] ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[10] ; LFEG[11] ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; LFEG[11] ; LFEG[12] ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
+-------+----------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+----------+-------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To    ; From Clock ;
+-------+--------------+------------+----------+-------+------------+
; N/A   ; None         ; 8.000 ns   ; LFEG[1]  ; L[1]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; LFEG[12] ; L[12] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; LFEG[11] ; L[11] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; LFEG[10] ; L[10] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; LFEG[9]  ; L[9]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; LFEG[8]  ; L[8]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; LFEG[7]  ; L[7]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; LFEG[6]  ; L[6]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; LFEG[5]  ; L[5]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; LFEG[4]  ; L[4]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; LFEG[3]  ; L[3]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; LFEG[2]  ; L[2]  ; CLK        ;
+-------+--------------+------------+----------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue May 20 13:23:19 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LEDWALK -c LEDWALK
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 76.92 MHz between source register "LFEG[1]" and destination register "LFEG[2]" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC67; Fanout = 3; REG Node = 'LFEG[1]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC65; Fanout = 3; REG Node = 'LFEG[2]'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC65; Fanout = 3; REG Node = 'LFEG[2]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC67; Fanout = 3; REG Node = 'LFEG[1]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock "CLK" to destination pin "L[1]" through register "LFEG[1]" is 8.000 ns
    Info: + Longest clock path from clock "CLK" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC67; Fanout = 3; REG Node = 'LFEG[1]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC67; Fanout = 3; REG Node = 'LFEG[1]'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_45; Fanout = 0; PIN Node = 'L[1]'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue May 20 13:23:20 2008
    Info: Elapsed time: 00:00:03