📄 traffic.fit.rpt
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+---------------------------------------------------------------------+
; Global & Other Fast Signals ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; CLK ; PIN_83 ; 1 ; On ; -- ;
+------+----------+---------+----------------------+------------------+
+---------------------------------------+
; Non-Global High Fan-Out Signals ;
+-----------------------------+---------+
; Name ; Fan-Out ;
+-----------------------------+---------+
; CLOCK ; 13 ;
; LTIME[4] ; 12 ;
; LTIME[3] ; 12 ;
; LTIME[2] ; 12 ;
; LTIME[1] ; 12 ;
; LTIME[0] ; 12 ;
; traffic|LSTATUS.state_bit_0 ; 11 ;
; traffic|LSTATUS.state_bit_1 ; 9 ;
; LREG[1] ; 2 ;
; LREG[4] ; 2 ;
; LREG[5] ; 2 ;
; LREG[2] ; 2 ;
; LREG[3] ; 2 ;
; LREG[6] ; 2 ;
+-----------------------------+---------+
+-----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 14 / 288 ( 5 % ) ;
; PIAs ; 22 / 288 ( 8 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 2.75) ; Number of LABs (Total = 2) ;
+----------------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 0 ;
; 12 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 1.75) ; Number of LABs (Total = 2) ;
+----------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+----------------------------------------+-----------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; D ; LC56 ; traffic|LSTATUS.state_bit_0, traffic|LSTATUS.state_bit_1, LTIME[4], LTIME[3], LTIME[2], LTIME[1], LTIME[0], LREG[6], CLOCK ; LREG[6], L[6] ;
; D ; LC49 ; traffic|LSTATUS.state_bit_0, traffic|LSTATUS.state_bit_1, LTIME[4], LTIME[3], LTIME[2], LTIME[1], LTIME[0], LREG[3], CLOCK ; LREG[3], L[3] ;
; D ; LC53 ; traffic|LSTATUS.state_bit_0, traffic|LSTATUS.state_bit_1, LTIME[4], LTIME[3], LTIME[2], LTIME[1], LTIME[0], LREG[5], CLOCK ; LREG[5], L[5] ;
; D ; LC51 ; traffic|LSTATUS.state_bit_0, traffic|LSTATUS.state_bit_1, LTIME[4], LTIME[3], LTIME[2], LTIME[1], LTIME[0], LREG[4], CLOCK ; LREG[4], L[4] ;
; E ; LC66 ; CLK ; LTIME[0], traffic|LSTATUS.state_bit_1, LTIME[1], LTIME[2], LTIME[3], LTIME[4], LREG[6], LREG[3], LREG[2], traffic|LSTATUS.state_bit_0, LREG[5], LREG[4], LREG[1] ;
; E ; LC68 ; CLOCK ; traffic|LSTATUS.state_bit_1, LTIME[1], LTIME[2], LTIME[3], LTIME[4], LREG[6], LREG[3], LREG[2], traffic|LSTATUS.state_bit_0, LREG[5], LREG[4], LREG[1] ;
; E ; LC69 ; traffic|LSTATUS.state_bit_0, LTIME[4], LTIME[3], LTIME[2], LTIME[1], LTIME[0], CLOCK ; LTIME[1], LTIME[2], LTIME[3], LREG[6], LREG[3], LREG[2], LREG[5], LREG[4], LREG[1] ;
; E ; LC70 ; traffic|LSTATUS.state_bit_0, traffic|LSTATUS.state_bit_1, LTIME[4], LTIME[3], LTIME[2], LTIME[1], LTIME[0], CLOCK ; traffic|LSTATUS.state_bit_1, LTIME[1], LTIME[2], LTIME[3], LTIME[4], LREG[6], LREG[3], LREG[2], traffic|LSTATUS.state_bit_0, LREG[5], LREG[4], LREG[1] ;
; E ; LC71 ; LTIME[4], LTIME[1], LTIME[0], LTIME[3], traffic|LSTATUS.state_bit_0, traffic|LSTATUS.state_bit_1, LTIME[2], CLOCK ; traffic|LSTATUS.state_bit_1, LTIME[1], LTIME[2], LTIME[3], LTIME[4], LREG[6], LREG[3], LREG[2], traffic|LSTATUS.state_bit_0, LREG[5], LREG[4], LREG[1] ;
; E ; LC72 ; LTIME[4], LTIME[2], LTIME[1], LTIME[0], traffic|LSTATUS.state_bit_0, traffic|LSTATUS.state_bit_1, LTIME[3], CLOCK ; traffic|LSTATUS.state_bit_1, LTIME[1], LTIME[2], LTIME[3], LTIME[4], LREG[6], LREG[3], LREG[2], traffic|LSTATUS.state_bit_0, LREG[5], LREG[4], LREG[1] ;
; E ; LC73 ; traffic|LSTATUS.state_bit_0, LTIME[3], LTIME[2], LTIME[1], LTIME[0], LTIME[4], CLOCK ; traffic|LSTATUS.state_bit_1, LTIME[1], LTIME[2], LTIME[3], LTIME[4], LREG[6], LREG[3], LREG[2], traffic|LSTATUS.state_bit_0, LREG[5], LREG[4], LREG[1] ;
; E ; LC65 ; traffic|LSTATUS.state_bit_0, traffic|LSTATUS.state_bit_1, LTIME[4], LTIME[3], LTIME[2], LTIME[1], LTIME[0], LREG[2], CLOCK ; LREG[2], L[2] ;
; E ; LC74 ; LTIME[4], LTIME[3], LTIME[2], LTIME[1], LTIME[0], CLOCK ; traffic|LSTATUS.state_bit_1, LTIME[1], LTIME[2], LTIME[3], LTIME[4], LREG[6], LREG[3], LREG[2], LREG[5], LREG[4], LREG[1] ;
; E ; LC67 ; traffic|LSTATUS.state_bit_0, traffic|LSTATUS.state_bit_1, LTIME[4], LTIME[3], LTIME[2], LTIME[1], LTIME[0], LREG[1], CLOCK ; LREG[1], L[1] ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+-----------------------------------------+
; Option ; Setting ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving an unspecified signal ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+-----------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue May 20 20:29:37 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off traffic -c traffic
Info: Selected device EPM7128SLC84-15 for design "traffic"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Tue May 20 20:29:38 2008
Info: Elapsed time: 00:00:04
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