📄 divdec.vhd
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----------------------------------------------------
--
-- VHDL code generated by Visual HDL
--
-- Design Unit:
-- ------------
-- Unit Name : DIV_DEC_CU
-- Library Name : my_eu
--
-- Creation Date : Wed Feb 06 00:38:59 2002
-- Version : 6.7.0.patch1-pc build 20 from Feb 20 2001
--
-- Options Used:
-- -------------
-- Target
-- HDL : VHDL
-- Purpose : Synthesis
-- Vendor : Synplify
--
-- Style
-- Use Procedures : No
-- Code Destination : 1 File per Unit
-- Attach Packages : No
-- Generate Entity : Yes
-- Attach Directives : Yes
-- Structural : No
-- Configuration Specification : No
-- library name in
-- Configuration Specification : No
-- Configuration Declaration : None
-- Preserve spacing for free text : Yes
-- Sort Ports by mode : No
-- Declaration alignment : No
--
----------------------------------------------------
----------------------------------------------------
--
-- Library Name : my_eu
-- Unit Name : DIV_DEC_CU
-- Unit Type : Text Unit
--
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.UPAC.all;
entity DIVDEC is
port( I_CLK : in std_logic;
I_RST : in std_logic;
I_DIVSTATE : in std_logic_vector( 3 downto 0);
I_BW : in std_logic;
I_RM : in std_logic_vector( 2 downto 0);
I_MOD : in std_logic_vector( 1 downto 0);
I_AAM : in std_logic; --control signal for AAM
I_QUOF : in std_logic;
I_IDIV : in std_logic; --signed div(idiv)
I_DIVCOUNT : in std_logic_vector( 4 downto 0);
I_SIGNPLS : in std_logic; --for idiv
I_SIGNTR2 : in std_logic; --for idiv
I_SIGNDIV : in std_logic; --for idiv
I_BSIGNDIV : in std_logic; --for idiv
O_TMPCS : out std_logic_vector( 4 downto 0); --for div tmpcs
O_BUSCS : out std_logic_vector( 4 downto 0);
O_GRRW : out std_logic;
O_GRSEL : out std_logic_vector( 3 downto 0);
O_DIVF : out std_logic;
O_QUOF : out std_logic;
O_ENDDIV : out std_logic; --for div end(<=1)
O_NEGA : out std_logic; --signset for answer
O_SCOUNT : out std_logic;
O_TYPEZERO : out std_logic; --type0 interrupt
O_DIVSTATE : out std_logic_vector( 3 downto 0) --for test
);
end DIVDEC;
architecture RTL of DIVDEC is
constant INITIAL : std_logic_vector(3 downto 0 ) := "0000";
constant AX_LD : std_logic_vector(3 downto 0 ) := "0011";
constant DATA_LD : std_logic_vector(3 downto 0 ) := "0001";
constant DX_LD : std_logic_vector(3 downto 0 ) := "0010";
constant MOD_ST : std_logic_vector(3 downto 0 ) := "1000";
constant Q_SET : std_logic_vector(3 downto 0 ) := "0111";
constant Q_ST : std_logic_vector(3 downto 0 ) := "1001";
constant SHIFT_L : std_logic_vector(3 downto 0 ) := "0101";
constant SIGN_SET : std_logic_vector(3 downto 0 ) := "1010";
constant SUB : std_logic_vector(3 downto 0 ) := "0110";
constant ZERO_SET : std_logic_vector(3 downto 0 ) := "0100";
signal signcheck : std_logic_vector(3 downto 0);
signal outsign : std_logic_vector(1 downto 0); --sign(quotient&odd)
signal quof : std_logic;
signal scount : std_logic;
signal typezero : std_logic;
signal tmpcsr : std_logic_vector(4 downto 0);
begin
O_DIVSTATE <= I_DIVSTATE; --for test
signcheck <= I_SIGNPLS&I_SIGNTR2&((I_SIGNDIV and I_BW) or (I_BSIGNDIV and (not I_BW)))&I_IDIV;--for signcheck
O_NEGA <= (outsign(1) or outsign(0)) and I_IDIV; --for fsm(to state a)
O_QUOF <= quof;
O_SCOUNT <= scount;
O_TYPEZERO <= typezero;
GRRW_OUT :
process (I_DIVSTATE)
begin
if (I_DIVSTATE = MOD_ST) then
O_GRRW <= '1';
elsif (I_DIVSTATE = Q_ST) then
O_GRRW <= '1';
else
O_GRRW <= '0';
end if;
end process;
DIVF_OUT :
process (I_DIVSTATE)
begin
if (I_DIVSTATE = INITIAL) then
O_DIVF <= '0';
else
O_DIVF <= '1';
end if;
end process;
END_DIVIDE_OUT :
process (I_DIVSTATE)
begin
if (I_DIVSTATE = Q_ST) then
O_ENDDIV <= '1'; --calculation finality
else
O_ENDDIV <= '0';
end if;
end process;
BUSCS_OUT :
process (I_DIVSTATE,I_MOD)
begin
case I_DIVSTATE is
when INITIAL =>
O_BUSCS <= "00000";
when DATA_LD =>
if (I_MOD= "11") then
O_BUSCS <= G2T2; --gr to tmp2
else
O_BUSCS <= B2T2; --biu to tmp2
end if;
when DX_LD =>
O_BUSCS <= G2T1; --biu to tmp1(plus_reg)
when AX_LD =>
O_BUSCS <= G2T2; -- gr to tmp2(reg2)
when ZERO_SET =>
O_BUSCS <= "00000";
when SHIFT_L =>
O_BUSCS <= "00000"; -- alu to tmp1
when SUB =>
O_BUSCS <= "00000";
when Q_SET =>
O_BUSCS <= A2T1; -- alu to tmp
when MOD_ST =>
O_BUSCS <= T12G; -- tmp1 to gr
when Q_ST =>
O_BUSCS <= T22G; -- tmp2 to gr
when SIGN_SET =>
O_BUSCS <= "00000";
when others =>
O_BUSCS <= "XXXXX";
end case;
end process;
GRSEL_OUT :
process (I_DIVSTATE,I_BW,I_RM,I_MOD,I_AAM)
begin
case I_DIVSTATE is
when INITIAL =>
O_GRSEL <= AX;
when DATA_LD =>
if (I_MOD= "11") then
O_GRSEL <= I_BW & I_RM;
else
O_GRSEL <= AX;
end if;
when DX_LD =>
O_GRSEL <= DX;
when AX_LD =>
if(I_AAM = '1')then
O_GRSEL <= AL;
else
O_GRSEL <= AX;
end if;
when ZERO_SET =>
O_GRSEL <= AX;
when SHIFT_L =>
O_GRSEL <= AX;
when SUB =>
O_GRSEL <= AX;
when Q_SET =>
O_GRSEL <= AX;
when MOD_ST =>
if (I_BW = '0') then
if(I_AAM = '1')then
O_GRSEL <= AL;
else
O_GRSEL <= AH;
end if;
else
O_GRSEL <= DX;
end if;
when Q_ST =>
if (I_BW = '0') then
if(I_AAM = '1')then
O_GRSEL <= AH;
else
O_GRSEL <= AL;
end if;
else
O_GRSEL <= AX;
end if;
when SIGN_SET =>
O_GRSEL <= AX;
when others =>
O_GRSEL <= "XXXX";
end case;
end process;
TMPCS_OUT :
process (I_DIVSTATE,I_BW,signcheck,outsign,tmpcsr)
begin
case I_DIVSTATE is
when INITIAL =>
O_TMPCS <= "00000";
when DATA_LD =>
O_TMPCS <= "00001";
when DX_LD =>
O_TMPCS <= "00110";
when AX_LD =>
O_TMPCS <= "00100";
when ZERO_SET =>
if (I_BW = '1') then
if (signcheck = "1111") then
O_TMPCS <= "11101";
elsif (signcheck = "1011") then
O_TMPCS <= "11101";
elsif (signcheck = "1001") then
O_TMPCS <= "11100";
elsif (signcheck = "1101") then
O_TMPCS <= "11100";
elsif (signcheck = "0011") then
O_TMPCS <= "11011";
elsif (signcheck = "0111") then
O_TMPCS <= "11011";
else
O_TMPCS <= "01001";
end if;
else
if (signcheck(2 downto 0) = "111") then
O_TMPCS <= "11010";
elsif (signcheck(2 downto 0) = "101") then
O_TMPCS <= "11000";
elsif (signcheck(2 downto 0) = "011") then
O_TMPCS <= "11001";
else
O_TMPCS <= "01000";
end if;
end if;
when SHIFT_L =>
O_TMPCS <= "01100";
when SUB =>
if (I_BW = '0') then
O_TMPCS <= "01110";
else
O_TMPCS <= "01101";
end if;
when Q_SET =>
if (I_BW = '0')then
O_TMPCS <= "01011";
else
O_TMPCS <= "01010";
end if;
when MOD_ST =>
if (I_BW = '0') then
O_TMPCS <= "00111";
else
O_TMPCS <= "00011";
end if;
when Q_ST =>
O_TMPCS <= "00101";
when SIGN_SET =>
if (I_BW = '0') then
if (outsign = "01") then
O_TMPCS <= "10010";
elsif (outsign = "10") then
O_TMPCS <= "10011";
elsif (outsign = "11") then
O_TMPCS <= "10101";
else
O_TMPCS <= tmpcsr;
end if;
else
if (outsign = "01") then
O_TMPCS <= "10001";
elsif (outsign = "10") then
O_TMPCS <= "10011";
elsif (outsign = "11") then
O_TMPCS <= "10000";
else
O_TMPCS <= tmpcsr;
end if;
end if;
when others =>
O_TMPCS <= "XXXXX";
end case;
end process;
tmpcsr_REG :
process (I_CLK,I_RST,I_DIVSTATE)
begin
if (I_RST = RST_ACT) then
tmpcsr <= "00000";
elsif (I_CLK'event and I_CLK = '0') then
if (I_DIVSTATE = INITIAL)then
tmpcsr <= "00000";
elsif (I_DIVSTATE = Q_SET )then
if (I_BW = '0')then
tmpcsr <= "01011";
else
tmpcsr <= "01010";
end if;
end if;
end if;
end process;
QUOF_REG :
process (I_DIVSTATE,I_CLK,I_RST,I_QUOF)
begin
if (I_RST = RST_ACT) then
quof <= '0';
elsif (I_CLK'event and I_CLK = '0') then
if (I_DIVSTATE = INITIAL) then
quof <= '0';
elsif (I_DIVSTATE = Q_SET) then
quof <= I_QUOF;
end if;
end if;
end process;
SCOUNT_REG :
process (I_DIVSTATE,I_CLK,I_RST)
begin
if (I_RST = RST_ACT) then
scount <= '0';
elsif (I_CLK'event and I_CLK = '0') then
if (I_DIVSTATE = INITIAL) then
scount <= '0';
elsif (I_DIVSTATE = SHIFT_L) then
scount <= '1';
elsif (I_DIVSTATE = SUB) then
scount <= '0';
end if;
end if;
end process;
typezero_interrupt_REG :
process (I_DIVSTATE,I_CLK,I_RST,I_BW,I_IDIV,I_DIVCOUNT,I_QUOF)
begin
if (I_RST = RST_ACT) then
typezero <= '0';
elsif (I_CLK'event and I_CLK = '0') then
if (I_DIVSTATE = INITIAL) then
typezero <= '0';
elsif (I_DIVSTATE = Q_SET) then
if (I_BW = '0') then
if (I_IDIV = '1') then --for type0 interrupt
if (I_DIVCOUNT < "01010") then --(idiv)
if (I_QUOF = '1') then
typezero <= '1';
end if;
end if;
else --(div)
if (I_DIVCOUNT < "01001") then
if (I_QUOF = '1') then
typezero <= '1';
end if;
end if;
end if;
else
if (I_IDIV ='1') then
if (I_DIVCOUNT < "10010") then
if (I_DIVCOUNT = "00000") then
typezero <= '0';
elsif (I_QUOF = '1') then
typezero <= '1';
end if;
end if;
else
if (I_DIVCOUNT < "10001") then
if (I_DIVCOUNT = "00000") then
typezero <= '0';
elsif (I_QUOF = '1') then
typezero <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
end process;
outsign_REG :
process (I_RST,I_CLK,I_DIVSTATE,I_BW,I_SIGNDIV,I_SIGNPLS,I_BSIGNDIV,I_SIGNTR2)
begin
if (I_RST = RST_ACT) then
outsign <= "00";
elsif (I_CLK'event and I_CLK = '0') then
if (I_DIVSTATE = INITIAL) then
outsign <= "00";
elsif (I_DIVSTATE = ZERO_SET) then
if (I_BW = '1') then
outsign <= (I_SIGNPLS XOR I_SIGNDIV ) & I_SIGNPLS; --for sign
else
outsign <= (I_SIGNTR2 XOR I_BSIGNDIV) & I_SIGNTR2; --for sign
end if;
end if;
end if;
end process;
end RTL;⌨️ 快捷键说明
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