truio.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TRUIO is
    port( I_REG3   :  in std_logic;
          I_TMPCS  :  in std_logic_vector( 4 downto 0 );
          I_DIVF   :  in std_logic;
          I_TMPRW  :  in std_logic_vector( 1 downto 0 );
	 	  I_MULCS  :  in std_logic_vector( 1 downto 0 );	
          O_TMPCS  : out std_logic_vector( 4 downto 0 )
		  );
end TRUIO;

architecture RTL of TRUIO is
begin
	process(I_REG3,I_TMPCS,I_DIVF,I_TMPRW,I_MULCS)
	begin
		if   (I_DIVF = '1')then
			O_TMPCS <= I_TMPCS;
		elsif(I_MULCS = "10")then
			O_TMPCS <= "01110";	
		else
			case I_TMPRW is
			when "01" => 
				O_TMPCS <= "00101"; --read reg2
			when "10" =>
				if (I_REG3 = '1')then
					O_TMPCS <= "00111"; --read reg3(plus_reg)
				else
					O_TMPCS <= "00011"; --read reg1
				end if;
			when "00" => 
				if(I_REG3 = '1')then
					O_TMPCS <= "11110"; --read reg3(plus_reg) or reg2
				else
					O_TMPCS <= "11111"; --read reg1 or reg2
				end if;
			when others	=> 
				O_TMPCS <= "00000"; --guard
			end case;
		end if;
	end process;

end RTL;