fetch.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library synplify;
use synplify.attributes.all;

entity FETCH is
	port( I_CLK      :  in std_logic;
          I_RST      :  in std_logic;
          I_RDQUE    :  in std_logic;
          I_DATA     :  in std_logic_vector(15 downto 0 );
          I_ODD      :  in std_logic;
          I_QUEF     :  in std_logic;
          I_QUERST   :  in std_logic;
          I_EUCRST   :  in std_logic;
          O_BDATA    : out std_logic_vector(7 downto 0 );
          O_FE       : out std_logic;
          O_CQUEF    : out std_logic;
          O_QUEEMPTY : out std_logic;
          O_QUEFULL  : out std_logic
          ); 
end FETCH;

architecture RTL of FETCH is

signal CQUE_BDATA : std_logic_vector( 7 downto 0);
signal CQUE_WR_N  : std_logic;
signal CQUE_WRQUE : std_logic;

component FIFO
	generic( WORD : integer := 6;
    	     K    : integer := 8 );             
    port( I_CLK      :  in std_logic;
		  I_RST      :  in std_logic;
		  I_QUERST   :  in std_logic; --Que reset signal
	      I_QUEWR_N  :  in std_logic; --write signal (furonri)
	      I_RDQUE    :  in std_logic; --read signal
		  I_CQUEF    :  in std_logic; --write QUE => '1'
    	  I_BDATA    :  in std_logic_vector(K-1 downto 0); --input instruction code
          O_BDATA    : out std_logic_vector(K-1 downto 0); --output instruction code
          O_FE       : out std_logic; --fetch signal
		  O_CQUEF    : out std_logic; --end write QUE => '1'
		  O_QUEFULL  : out std_logic; --full flag
          O_QUEEMPTY : out std_logic  --empty flag
		  ); 
end component;

component CQUE
    port( I_CLK     :  in std_logic;
          I_RST     :  in std_logic;
		  I_EUCRST  :  in std_logic; --from EUC reset signal
          I_DATA    :  in std_logic_vector(15 downto 0); --IN DATA form DC
          I_QUEF    :  in std_logic; --DATA out flag from DC
		  I_ODD     :  in std_logic; --I_ADR(0)='1'(odd) => '1'
		  O_QUEWR_N : out std_logic; --negative write signal to QUE
		  O_CQUEF   : out std_logic; --write QUE =>> '1'
          O_BDATA   : out std_logic_vector( 7 downto 0) --DATA out to QUE
		  ); 
end component; 

begin 
	FIFO_FETCH : FIFO
	generic map( 
		WORD => 6,
    	K => 8
		)             
    port map( 
		I_CLK => I_CLK, 
		I_RST => I_RST,
		I_QUERST => I_QUERST,
	    I_QUEWR_N => CQUE_WR_N,
	    I_RDQUE => I_RDQUE,
		I_CQUEF => CQUE_WRQUE,
    	I_BDATA => CQUE_BDATA,
        O_BDATA => O_BDATA,
        O_FE => O_FE,
		O_CQUEF => O_CQUEF,
		O_QUEFULL => O_QUEFULL,
        O_QUEEMPTY => O_QUEEMPTY
		); 

	CQUE_FETCH : CQUE
    port map( 
		I_CLK => I_CLK,
        I_RST => I_RST,
		I_EUCRST => I_EUCRST,
        I_DATA => I_DATA,
        I_QUEF => I_QUEF,
		I_ODD => I_ODD,
		O_QUEWR_N => CQUE_WR_N,
		O_CQUEF => CQUE_WRQUE,
        O_BDATA => CQUE_BDATA
		); 

end RTL;