gru.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.UPAC.all;

entity GRU is
	port( I_CLK   :  in std_logic;
		  I_RST   :  in std_logic;
          I_S77   :  in std_logic;
          I_GRRW  :  in std_logic;
          I_GRSEL :  in std_logic_vector( 3 downto 0 );
     	  I_GREG  :  in std_logic_vector(15 downto 0 );
		  O_GREG  : out std_logic_vector(15 downto 0 );
		  O_AX_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_BX_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_CX_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_DX_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_SP_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_BP_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_DI_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_SI_V  : out std_logic_vector(15 downto 0 ) --for test
		  );
end GRU;

architecture RTL of GRU is

signal ah_v : std_logic_vector(7 downto 0);
signal al_v : std_logic_vector(7 downto 0);
signal bh_v : std_logic_vector(7 downto 0);
signal bl_v : std_logic_vector(7 downto 0);
signal ch_v : std_logic_vector(7 downto 0);
signal cl_v : std_logic_vector(7 downto 0);
signal dh_v : std_logic_vector(7 downto 0);
signal dl_v : std_logic_vector(7 downto 0);
signal sp_v : std_logic_vector(15 downto 0);
signal bp_v : std_logic_vector(15 downto 0);
signal di_v : std_logic_vector(15 downto 0);
signal si_v : std_logic_vector(15 downto 0);
signal d_o	: std_logic_vector(15 downto 0);

begin
	process(I_GRRW,d_o)
	begin
		if (I_GRRW = '0')then
			O_GREG <= d_o;
		else
			O_GREG <= "ZZZZZZZZZZZZZZZZ";
		end if;
	end process;

	O_AX_V <= ah_v & al_v;	--for test(AX~SI)
	O_BX_V <= bh_v & bl_v;              
	O_CX_V <= ch_v & cl_v;
	O_DX_V <= dh_v & dl_v;
	O_SP_V <= sp_v;
	O_BP_V <= bp_v;
	O_DI_V <= di_v;
	O_SI_V <= si_v;

 	AH_GR :
	process(I_CLK,I_S77,I_RST,I_GRRW,I_GRSEL,I_GREG)
	begin
		if (I_RST = RST_ACT) then
			ah_v <= "10000011";
		elsif (I_CLK'event and I_CLK = '0')then
			if (I_S77 = '1') then
				if (I_GRRW = '1') then
					if    (I_GRSEL = AX) then
						ah_v <= I_GREG(15 downto 8 );
					elsif (I_GRSEL = AH) then
						ah_v <= I_GREG( 7 downto 0 );
					end if;
				end if;
			end if;
		 end if;
	end process;

 	AL_GR :
	process(I_CLK,I_S77,I_RST,I_GRRW,I_GRSEL,I_GREG(7 downto 0))
	begin
		if (I_RST = RST_ACT) then
			al_v <= "10000001";
		elsif (I_CLK'event and I_CLK = '0')then
			if (I_S77 = '1') then
				if (I_GRRW = '1') then
					if    (I_GRSEL = AX) then
						al_v <= I_GREG( 7 downto 0 );
					elsif (I_GRSEL = AL) then 
						al_v <= I_GREG( 7 downto 0 );
					end if;
				end if;
			end if;
		 end if;
	end process;

 	BH_GR :
	process(I_CLK,I_S77,I_RST,I_GRRW,I_GRSEL,I_GREG)
	begin
		if (I_RST = RST_ACT) then
			bh_v <= "00000011";
		elsif (I_CLK'event and I_CLK = '0')then
			if (I_S77 = '1') then
				if (I_GRRW = '1') then
					if    (I_GRSEL = BX) then
						bh_v <= I_GREG(15 downto 8 );
					elsif (I_GRSEL = BH) then
						bh_v <= I_GREG( 7 downto 0 );
					end if;
				end if;
			end if;
		end if;
	end process;

 	BL_GR :
	process(I_CLK,I_S77,I_RST,I_GRRW,I_GRSEL,I_GREG(7 downto 0))
	begin
		if (I_RST = RST_ACT) then
			bl_v <= "00000001";
		elsif (I_CLK'event and I_CLK = '0')then
			if (I_S77 = '1') then
				if (I_GRRW = '1') then
					if    (I_GRSEL = BX) then
						bl_v <= I_GREG( 7 downto 0 );
					elsif (I_GRSEL = BL) then
						bl_v <= I_GREG( 7 downto 0 );
					end if;
				end if;
			 end if;
		end if;
	end process;

 	CH_GR :
	process(I_CLK,I_S77,I_RST,I_GRRW,I_GRSEL,I_GREG)
	begin
		if (I_RST = RST_ACT) then
			ch_v <= "00000000";
		elsif (I_CLK'event and I_CLK = '0')then
			if (I_S77 = '1') then
				if (I_GRRW = '1') then
					if    (I_GRSEL = CX) then
						ch_v <= I_GREG(15 downto 8 );
					elsif (I_GRSEL = CH) then
						ch_v <= I_GREG( 7 downto 0 );
					end if;
				end if;
			 end if;
		end if;
	end process;

 	CL_GR :
	process(I_CLK,I_S77,I_RST,I_GRRW,I_GRSEL,I_GREG(7 downto 0))
	begin
		if (I_RST = RST_ACT) then
			cl_v <= "00000010";
		elsif (I_CLK'event and I_CLK = '0')then
			if (I_S77 = '1') then
				if (I_GRRW = '1') then
					if    (I_GRSEL = CX) then
						cl_v <= I_GREG( 7 downto 0 );
					elsif (I_GRSEL = CL) then
						cl_v <= I_GREG( 7 downto 0 );
					end if;
				end if;
			 end if;
		end if;
	end process;

 	DH_GR :
	process(I_CLK,I_S77,I_RST,I_GRRW,I_GRSEL,I_GREG)
	begin
		if (I_RST = RST_ACT) then
			dh_v <= "00000000";
		elsif (I_CLK'event and I_CLK = '0')then
			if (I_S77 = '1') then
				if (I_GRRW = '1') then
					if    (I_GRSEL = DX) then
						dh_v <= I_GREG(15 downto 8 );
					elsif (I_GRSEL = DH) then
						dh_v <= I_GREG( 7 downto 0 );
					end if;
				end if;
			 end if;
		end if;
	end process;

 	DL_GR :
	process(I_CLK,I_S77,I_RST,I_GRRW,I_GRSEL,I_GREG(7 downto 0))
	begin
		if (I_RST = RST_ACT) then
			dl_v <= "11111111";
		elsif (I_CLK'event and I_CLK = '0')then
			if (I_S77 = '1') then
				if (I_GRRW = '1') then
					if    (I_GRSEL = DX) then
						dl_v <= I_GREG( 7 downto 0 );
					elsif (I_GRSEL = DL) then
						dl_v <= I_GREG( 7 downto 0 );
					end if;
				end if;
			end if;
		end if;
	end process;

 	SP_GR :
	process(I_CLK,I_S77,I_RST,I_GRRW,I_GRSEL,I_GREG)
	begin
		if (I_RST = RST_ACT) then
			sp_v <= "0000000000000011";
		elsif (I_CLK'event and I_CLK = '0')then
			if (I_S77 = '1') then
				if (I_GRRW = '1') then
					if (I_GRSEL = SP) then
						sp_v <= I_GREG(15 downto 0);
					end if;
				end if;
			end if;
		 end if;
	end process;

 	BP_GR :
	process(I_CLK,I_S77,I_RST,I_GRRW,I_GRSEL,I_GREG)
	begin
		if (I_RST = RST_ACT) then
			bp_v <= "0000000000000011";
		elsif (I_CLK'event and I_CLK = '0')then
			if (I_S77 = '1') then
				if (I_GRRW = '1') then
					if (I_GRSEL = BP) then
						bp_v <= I_GREG(15 downto 0);
					end if;
				end if;
			end if;
		 end if;
	end process;

 	DIX_GR :
	process(I_CLK,I_S77,I_RST,I_GRRW,I_GRSEL,I_GREG)
	begin
		if (I_RST = RST_ACT) then
			di_v <= "0000000000000011";
		elsif (I_CLK'event and I_CLK = '0')then
			if (I_S77 = '1') then
				if (I_GRRW = '1') then
					if (I_GRSEL = DIX) then
						di_v <= I_GREG(15 downto 0);
					end if;
				end if;
			end if;
		 end if;
	end process;

 	SIX_GR :
	process(I_CLK,I_S77,I_RST,I_GRRW,I_GRSEL,I_GREG)
	begin
		if (I_RST = RST_ACT) then
			si_v <= "0000000000000011";
		elsif (I_CLK'event and I_CLK = '0')then
			if (I_S77 = '1') then
				if (I_GRRW = '1') then
					if (I_GRSEL = SIX) then
						si_v <= I_GREG(15 downto 0);
					end if;
				end if;
			end if;
		 end if;
	end process;

	process(I_GRSEL,ah_v,al_v,bh_v,bl_v,ch_v,cl_v,dh_v,dl_v,sp_v,bp_v,di_v,si_v) 
	begin
		case I_GRSEL is
		when AX  => 
			d_o <= ah_v & al_v;
		when AH  => 
			d_o <= "00000000" & ah_v;
		when AL  => 
			d_o <= "00000000" & al_v;
		when BX  => 
			d_o <= bh_v & bl_v;       
		when BH  => 
			d_o <= "00000000" & bh_v;
		when BL  => 
			d_o <= "00000000" & bl_v;
		when CX  => 
			d_o <= ch_v & cl_v;
		when CH  => 
			d_o <= "00000000" & ch_v;
		when CL  => 
			d_o <= "00000000" & cl_v;
		when DX  => 
			d_o <= dh_v & dl_v;
		when DH  => 
			d_o <= "00000000" & dh_v;
		when DL  => 
			d_o <= "00000000" & dl_v;      
		when SP  => 
			d_o <= sp_v;
		when BP  => 
			d_o <= bp_v;
		when DIX => 
			d_o <= di_v;
		when SIX => 
			d_o <= si_v;
		when others => 
			d_o <= "XXXXXXXXXXXXXXXX";
		end case;
	end process;

end RTL;