ip.vhd

X8086的VHDL源码

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--   FILE NAME : IP_IPIR.vhd
--   FUNCTION  : Instruction pointer
--   AUTHOR    : Kazuma Mishima
--   DATE      : 5/2001
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.UPAC.all;

entity IP is
    port( I_CLK    :  in std_logic;
		  I_RST    :  in std_logic;
		  I_RDIP   :  in std_logic; --READ signal 
		  I_WRIP   :  in std_logic;
	      I_DATA   :  in std_logic_vector(15 downto 0); --input data
		  O_IPF    : out std_logic; --address out => '1'
		  O_IPDATA : out std_logic_vector(15 downto 0) --output data
		  );
end IP;

architecture RTL of IP is

signal ip  : std_logic_vector(15 downto 0); --IP register
signal nfe : std_logic_vector(15 downto 0); --next fetch IP

begin     

	O_IPF    <= I_RDIP; --address out flag
	O_IPDATA <= ip;
--INPUT
	INSTRUCTION_POINTER : 
	process(I_CLK,I_RDIP,I_RST,I_WRIP,I_DATA,nfe)
	begin
		if (I_RST = RST_ACT) then
			ip <= "0000000000000000";      
		elsif (I_CLK'event and I_CLK='0') then
		--WRITE to IP
			if (I_WRIP = '1') then
				ip <= I_DATA;       
  			else
				if (I_RDIP = '1') then  --read fetch
					ip <= nfe;
				end if;
			end if;
		end if;
	end process;
--next fetch offset
	NEXT_FETCH_OFFSET : 
	process(I_CLK,I_RST,I_WRIP,I_DATA,I_RDIP,nfe)
	begin
		if (I_RST = RST_ACT)then
			nfe <= "0000000000000000";
		elsif (I_CLK'event and I_CLK='0') then
			if (I_WRIP = '1') then
				nfe <= I_DATA;
			else
				if (I_RDIP = '1') then
					if (nfe(0) = '0') then --end fetch and address even
						nfe <= nfe + "0000000000000010"; --IP+2
					else
						nfe <= nfe + "0000000000000001"; --IP+1
					end if;
				end if;
			end if;
		end if;
	end process;
			  
end RTL;