mpx8in4outa.vhd

X8086的VHDL源码

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--   FILE NAME : DIV_MPX_BIU.vhd
--   FUNCTION  : select signal (from EUC or from DIV)
--   AUTHOR    : Kazuma Mishima
--   DATE      : 10/2001
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.UPAC.ALL;

entity MPX8IN4OUTA is
	generic( S1W : integer :=  4; --memory WORD
			 S2W : integer :=  5;
			 S3W : integer :=  4
			 --S4W : integer :=  0
			 ); 
    port( I_SW       :  in std_logic;
		  --I_DATA11   :  in std_logic_vector( S1W-1 downto 0 ); --I_SW=1
          I_DATA12   :  in std_logic_vector( S2W-1 downto 0 ); --I_SW=1
          I_DATA13   :  in std_logic_vector( S3W-1 downto 0 ); --I_SW=1
          I_DATA14   :  in std_logic;                          --I_SW=1
          I_DATA01   :  in std_logic_vector( S1W-1 downto 0 ); --I_SW=0
          I_DATA02   :  in std_logic_vector( S2W-1 downto 0 ); --I_SW=0
          I_DATA03   :  in std_logic_vector( S3W-1 downto 0 ); --I_SW=0
          I_DATA04   :  in std_logic;                          --I_SW=0
          O_DATA1    : out std_logic_vector( S1W-1 downto 0 );
          O_DATA2    : out std_logic_vector( S2W-1 downto 0 );
          O_DATA3    : out std_logic_vector( S3W-1 downto 0 );
          O_DATA4    : out std_logic
		  );
end MPX8IN4OUTA;

architecture RTL of MPX8IN4OUTA is

begin
	process(I_SW,I_DATA12,I_DATA13,I_DATA14,I_DATA01,I_DATA02,I_DATA03,I_DATA04)
	begin
--caluculate DIVID
		if(I_SW = '1')then 
			O_DATA1 <= GEN;
			O_DATA2 <= I_DATA12;
			O_DATA3 <= I_DATA13;
			O_DATA4 <= I_DATA14;
		else
			O_DATA1 <= I_DATA01;
			O_DATA2 <= I_DATA02;
			O_DATA3 <= I_DATA03;
			O_DATA4 <= I_DATA04;
		end if;
	end process;
end RTL;