sreg.vhd

X8086的VHDL源码

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--   FILE NAME : regst_REG.vhd
--   FUNCTION  : register
--   AUTHOR    : Kazuma Mishima
--   DATE      : 5/2001
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.UPAC.all;

entity SREG is
    generic( SEGWIDTH : integer ); 
    port( I_CLK       :  in std_logic;
	      I_RST       :  in std_logic;
	      I_DATA      :  in std_logic_vector(SEGWIDTH-1 downto 0 ); --register in
		  I_RDSR      :  in std_logic; --Read signal                             
		  I_WRSR      :  in std_logic; --write signal
		  I_RDIP      :  in std_logic; --read IP signal (FETCH)     
     	  I_SRSEL     :  in std_logic_vector( 1 downto 0 );--Signal to select a segment
		  O_SREGDATA  : out std_logic_vector(SEGWIDTH-1 downto 0 ); --register out
		  O_CS_V      : out std_logic_vector(SEGWIDTH-1 downto 0 );
          O_DS_V      : out std_logic_vector(SEGWIDTH-1 downto 0 );
		  O_SS_V      : out std_logic_vector(SEGWIDTH-1 downto 0 );
		  O_ES_V      : out std_logic_vector(SEGWIDTH-1 downto 0 )
		  ); 
end SREG;

architecture RTL of SREG is

signal cs_v : std_logic_vector(SEGWIDTH-1 downto 0);
signal ds_v : std_logic_vector(SEGWIDTH-1 downto 0);
signal ss_v : std_logic_vector(SEGWIDTH-1 downto 0);
signal es_v : std_logic_vector(SEGWIDTH-1 downto 0);
signal dt   : std_logic_vector(SEGWIDTH-1 downto 0);

begin
	O_SREGDATA <= dt;
	O_CS_V     <= cs_v ;
	O_DS_V     <= ds_v ;
	O_SS_V     <= ss_v ;
	O_ES_V     <= es_v ;

--write register 
	Code_Segment_Register:
	process(I_CLK,I_RST,I_WRSR,I_SRSEL,I_DATA)
	begin
		if (I_RST = RST_ACT) then
			cs_v <= (others => '1');
		elsif (I_CLK'event and I_CLK='0') then
			if (I_WRSR='1') then
				if (I_SRSEL = CS) then --CS
					cs_v <= I_DATA;
				end if;
			end if;
		end if;
	end process;

	Data_Segment_Register:
	process(I_CLK,I_RST,I_WRSR,I_SRSEL,I_DATA)
	begin
		if (I_RST = RST_ACT) then
			ds_v <= (others => '0');
		elsif (I_CLK'event and I_CLK='0') then
			if (I_WRSR='1') then
				if (I_SRSEL = DS) then --DS
					ds_v <= I_DATA;
				end if;
			end if;
		end if;
	end process;

	Stack_Segment_Register:
	process(I_CLK,I_RST,I_WRSR,I_SRSEL,I_DATA)
	begin
		if (I_RST = RST_ACT) then
			ss_v <= (others => '0');
		elsif (I_CLK'event and I_CLK='0') then
			if (I_WRSR='1') then
				if (I_SRSEL = SS) then --SS
					ss_v <= I_DATA;
				end if;
			end if;
		end if;
	end process;

	Extra_Segment_Register:
	process(I_CLK,I_RST,I_WRSR,I_SRSEL,I_DATA)
	begin
		if (I_RST = RST_ACT) then
			es_v <= (others => '0');
		elsif (I_CLK'event and I_CLK='0') then
			if (I_WRSR='1') then
				if (I_SRSEL = ES) then --ES
					es_v <= I_DATA;
				end if;
			end if;
		end if;
	end process;

--read register
	ReadRegister :
	process(I_CLK,I_RST,I_RDIP,I_RDSR,I_SRSEL,cs_v,ds_v,ss_v,es_v)
	begin
		if (I_RST = RST_ACT) then
			dt <= (others => '0');
		elsif (I_CLK'event and I_CLK='0')then 
			if (I_RDIP='1') then
				dt <= cs_v;
			else
				if (I_RDSR='1')then --register read 
					case I_SRSEL is
					when "01" => 
						dt <= cs_v; --CS
					when "11" => 
						dt <= ds_v; --DS
					when "10" => 
						dt <= ss_v; --SS
					when "00" => 
						dt <= es_v; --ES
					when others => 
						dt <= (others => 'X');
					end case;
				end if;
			end if;
		end if;
	end process;

end RTL;