stdec.vhd

X8086的VHDL源码

library ieee; use ieee.STD_LOGIC_1164.all;
use work.UPAC.all;

entity STDEC is
	port( I_MOD			:  in std_logic_vector( 1 downto 0 ); --mod in op code 
		  I_RM	        :  in std_logic_vector( 2 downto 0 ); --rm in op code
		  I_BW			:  in std_logic; --byte or word
		  I_EACUSTATE   :  in std_logic_vector( 2 downto 0 ); --EA state
	      O_EACUSTATE_V : out std_logic_vector( 2 downto 0 ); --for test
		  O_EARQ	    : out std_logic; --mem(EA)value request 
		  O_RDQUE	    : out std_logic; --read que signal
		  O_SE          : out std_logic; --disp sign extension(<='1') 
		  O_TMPRW	    : out std_logic_vector( 1 downto 0 ); --TMPreg read or write(00:read,01:tmp1 write,10:tmp2 write,11:write)
		  O_D16HL	    : out std_logic; --displacement-high or low
		  O_BUSCS	    : out std_logic_vector( 4 downto 0 ); --bus cotrol
		  O_GRSEL	    : out std_logic_vector( 3 downto 0 )   --GR select
		  ); 
end;

architecture rtl of STDEC is

constant INITIAL  : std_logic_vector(2 downto 0 ) := "000";
constant D16      : std_logic_vector(2 downto 0 ) := "001";
constant ALU_OUT  : std_logic_vector(2 downto 0 ) := "010";
constant DATA1    : std_logic_vector(2 downto 0 ) := "011";
constant DATA2    : std_logic_vector(2 downto 0 ) := "100";
constant DATA3    : std_logic_vector(2 downto 0 ) := "101";
constant DATA_OUT : std_logic_vector(2 downto 0 ) := "110";
constant TMP_DATA : std_logic_vector(2 downto 0 ) := "111";

begin
	O_EACUSTATE_V <= I_EACUSTATE ; --for test

	D16HL_OUT :
	process (I_EACUSTATE)
	begin	
		if (I_EACUSTATE = D16) then
			O_D16HL <= '1';
		else
			O_D16HL <= '0';
		end if;
	end process;

	EARQ_OUT : 
	process (I_EACUSTATE)
	begin
		if    (I_EACUSTATE = ALU_OUT) then
			O_EARQ  <= '1'; --mem request
		elsif (I_EACUSTATE = DATA_OUT)then
			O_EARQ  <= '1'; --mem request
		else
			O_EARQ  <= '0';
		end if;
	end process;

	SignExtention_OUT :
	process (I_EACUSTATE,I_MOD)
	begin		
		if (I_EACUSTATE = DATA2) then
			if (I_MOD = "01")then
				O_SE <= '1';
			else
				O_SE <= '0';
			end if;
		else
			O_SE <= '0';
		end if;
	end process;

	BUSCS_OUT : 
	process (I_EACUSTATE,I_MOD,I_RM)
	begin
		case I_EACUSTATE is
		when INITIAL => 
			O_BUSCS <= "00000";
		when DATA1 => --data1
			if (I_MOD = "00") then
				if (I_RM = "110") then
					O_BUSCS <= "00000";
				else
					O_BUSCS <= G2T1; --gr2tmp1
				end if;
			else
				O_BUSCS <= G2T1; --gr2tmp1
			end if;
		when DATA2 => --data2
			if    (I_MOD = "00" )then
				if    (I_RM = "000" or I_RM = "010") then
				    O_BUSCS <= G2T2; --gr2tmp2
				elsif (I_RM = "001" or I_RM = "011") then 
				    O_BUSCS <= G2T2; --gr2tmp2
				elsif (I_RM = "110") then 
				    O_BUSCS <= B2T2; --biu(q)2tmp2
				else 
				    O_BUSCS <= "00000";							
				end if;		
			elsif (I_MOD = "01")then 
				O_BUSCS <= "11101"; --biu(q)2tmp2	
			elsif (I_MOD = "10")then
				O_BUSCS <= "11101";
			else
				O_BUSCS <= "00000";
			end if;
		when D16 => --D16
			O_BUSCS <= B2T2;
		when TMP_DATA => --tmp_data
			O_BUSCS <= A2T2; --alu2tmp2
		when DATA3 => --data3
			O_BUSCS <= G2T1; --gr2tmp1
		when ALU_OUT => --alu_out
			if (I_MOD = "00") then
				if (I_RM = "110") then
	            	O_BUSCS <= T22B; --tmp2 to biu
	            else
					O_BUSCS <= A2B; --alu2biu
	            end if;
			else
	        		O_BUSCS <= A2B; --alu2biu
			end if;
		when DATA_OUT => --data_out(reg)
			O_BUSCS <= G2B;	--gr2biu
		when others => 
			O_BUSCS <= "XXXXX";
		end case;
	end process;

	TMPRW_OUT : 
	process (I_EACUSTATE,I_MOD,I_RM)
	begin		
		case I_EACUSTATE is
		when INITIAL => 
			O_TMPRW <= "00";
		when DATA1 => --data1
			if (I_MOD = "00") then
				if (I_RM = "110") then
					O_TMPRW <= "00";
				else
					O_TMPRW <= "01";
				end if;
			else
				O_TMPRW <= "01";
			end if;
		when DATA2 => --data2
			O_TMPRW <= "10";
		when D16 => --D16
			O_TMPRW <= "10";			
		when TMP_DATA => --tmp_data
			O_TMPRW <= "10";
		when DATA3 => --data3
			O_TMPRW <= "01";
		when ALU_OUT => --alu_out
			O_TMPRW <= "00";
		when DATA_OUT => --data_out(reg)
			O_TMPRW <= "00";
		when others => 
			O_TMPRW <= "XX";
		end case;
	end process;

	RDQUE_OUT : 
	process (I_EACUSTATE,I_MOD,I_RM,I_BW)
	begin
		if    (I_EACUSTATE = DATA1) then
 		    if    (I_MOD = "01" or I_MOD = "10") then
				O_RDQUE <= '1'; --for dislacement(8bit or 16bit(low))
			elsif (I_MOD = "00") then
				if (I_RM = "110") then
					O_RDQUE <= '1';
				else
					O_RDQUE <= '0';
				end if;
			else 
					O_RDQUE <= '0';
			end if;
		elsif (I_EACUSTATE = DATA2)then
			if    (I_MOD = "00") then
 				if (I_RM = "110") then
				    if (I_BW = '1') then
				    	O_RDQUE <= '1';
				    else
				    	O_RDQUE <= '0';
				    end if;
				else
				    O_RDQUE <= '0';
				end if;
			elsif (I_MOD = "10")then 
				O_RDQUE <= '1'; --for 16bit displacement(high)
			else
				O_RDQUE <= '0';
			end if;
		else
			O_RDQUE <= '0';
		end if;
	end process;

	GRSEL_OUT : 
	process (I_EACUSTATE,I_MOD,I_RM)
	begin		
		case I_EACUSTATE is
		when INITIAL => 
			O_GRSEL <= SIX;
		when DATA1 => --data1
			case I_RM is
			when "000" | "001" | "111" => 
				O_GRSEL <= BX;
			when "010" | "011" | "110" => 
				O_GRSEL <= BP;
			when "100" => 
				O_GRSEL <= SIX;
			when "101" => 
				O_GRSEL <= DIX;
			when others => 
				O_GRSEL <= SIX;
			end case;
		when DATA2 => --data2 
			case I_MOD is
			when "00" => 	
				case I_RM is
				when "000" | "010" => 
					O_GRSEL <= SIX;
				when "001" | "011" => 
					O_GRSEL <= DIX;
				when "110" => 
					O_GRSEL <= SIX;	
				when others => 
					O_GRSEL <= SIX;								
				end case;		
			when "01" => 
				O_GRSEL <= SIX;
			when "10" => 
				O_GRSEL <= SIX;
			when others => 
				O_GRSEL <= SIX;
			end case;
		when D16 => --D16
			O_GRSEL <= SIX;			
		when TMP_DATA => --tmp_data
			O_GRSEL <= SIX;
		when DATA3 => --data3
			case I_RM is
			when "000" | "010" => 
				O_GRSEL <= SIX;
			when "001" | "011" => 
				O_GRSEL <= DIX;
			when others => 
				O_GRSEL <= SIX;
			end case;
		when ALU_OUT => --alu_out
			O_GRSEL <= SIX;
		when DATA_OUT => --data_out(reg)
			case I_RM is
			when "100" => 
				O_GRSEL <= SIX;
			when "101" => 
				O_GRSEL <= DIX;
			when "111" => 
				O_GRSEL <= BX;
			when others => 
				O_GRSEL <= SIX;
			end case;
		when others => 
			O_GRSEL <= "XXXX";
		end case;
	end process;

end;