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-- O_ALUCS <= GEN;
-- EUC_ST <= "0110";
-- when SUBie_c =>
-- null; --wait state for check empty
-- when SUBie4_2 => null;
-- -- EUC_ST <= "0111";
-- when SUBie4_3 =>
-- EUC_ST <= "1000";
-- if(d = '0' and bw = '1')then
-- O_D16HL <= '1'; --16bit data
-- elsif(d = '1' and bw = '1')then
-- O_SE <= '1'; --sign extension(8bit=>16bit)
-- else
-- null;
-- end if;
-- write
-- when SUBie5 =>
-- O_RD <= '0';
-- EUC_ST <= "1001";
-- if(reg = "011")then --for SBBie
-- O_USECARRY <= '1';
-- end if;
-- if(reg /= "111")then
-- if(modo /= "11")then --result => ea
-- O_TMPRW <= "00"; --no writing
-- O_BUSCS <= A2B; --out data ALU => BIU
-- O_WR <= '1';
-- else --result => ea
-- O_GRRW <= '1'; --write GR
-- O_BUSCS <= A2G; --ALU => GR
-- O_TMPRW <= "00"; --read tmpREG1
-- O_GRSEL <= bw & rm; --set GR
-- O_FREN <= "000101010000000000"; --FR set
-- end if;
-- else
-- O_FREN <= "000101010000000000"; --FR set
-- end if;
-- when SUBie6 =>
-- O_FREN <= "000101010000000000"; --FR set
-- -- EUC_ST <= "1010";
--immediate to accumulator(ADDia,ADCia)
--input op code
-- when SUBia1 => null;
-- EUC_ST <= "0011";
--calculate EA
-- when SUBia2 => --output byte or word
-- EUC_ST <= "0100";
-- O_ALUCS <= GEN;
-- O_GRRW <= '0'; --read GR
-- O_BUSCS <= G2T1; --GR => tmpREG1
-- O_TMPRW <= "01"; --write tmpREG1
-- O_GRSEL <= bw & "000"; --set GR
--read immediate data
-- when SUBia3 => null;
-- EUC_ST <= "0101";
-- when SUBia_c =>
-- EUC_ST <= "0110";
-- null; --wait state for check empty
-- when SUBia4 =>
-- EUC_ST <= "0111";
-- tmpv := I_BDATA(7 downto 0);
-- when SUBia5 =>
--- O_DATA <= I_BDATA(7 downto 0) & tmp ;
-- if(op(7 downto 1) = SBBia)then
-- O_USECARRY <= '1';
-- end if;
-- O_2EU <='1';
-- O_BUSCS <= B2T2 ; --tmpREG2 <= data
-- O_ALUCS <= GEN ;
-- O_TMPRW <= "10"; --write tmpREG2
-- O_RD <= '0';
-- EUC_ST <= "1000";
-- write
-- when SUBia6 =>
-- O_ALUCS <= GEN ;
-- O_RD <= '0';
-- O_FREN <= "000101010000000000"; --FR set
-- EUC_ST <= "1001";
-- if(op(7 downto 1) = SBBia)then --for SBBia
-- O_USECARRY <= '1';
-- end if;
-- if(op(7 downto 1) /= CMPia)then
-- O_GRRW <= '1'; --write GR
-- O_BUSCS <= A2G; --ALU => GR
-- O_TMPRW <= "00"; --read tmpREG1
-- O_GRSEL <= bw & "000"; --set AX(AL)
-- end if;
--NEG-------------------------------------------------------------------
--calculate EA
when NEG1 =>
O_MOD <= I_BDATA(7 downto 6); --output mod
modov := I_BDATA(7 downto 6); --save mod
regv := I_BDATA(5 downto 3); --save reg
O_RM <= I_BDATA(2 downto 0); --output r/m
rmv := I_BDATA(2 downto 0); --save r/m
--output byte or word
-- EUC_ST <= "0100";
if(I_BDATA(7 downto 6)= "11")then --register
O_GRRW <= '0'; --read GR
O_BUSCS <= G2T1; --GR => tmpREG1
O_TMPRW <= "01"; --write tmpREG1
O_GRSEL <= bw & I_BDATA(2 downto 0); --set GR
O_ALUCS <= "1111"; --twos complement conversion
else --memory+1
O_EA <= '1'; --calculate EA
O_ALUCS <= KA; --ALU => ADD
end if;
--TTMPOUT <= I_BDATA(7 downto 0);
when NEG2 =>
if(modo /= "11")then
O_RD <= '1';
O_BUSCS <= B2T1; --memory => tmpREG1
O_EA <= '0';
O_TMPRW <= "01"; --write tmpREG1
end if;
-- EUC_ST <= "0101";
O_ALUCS <= "1111"; --twos complement conversion
-- write
--TTMPOUT <= I_BDATA(7 downto 0);
when NEG3 =>
O_ALUCS <= "1111"; --twos complement conversion
O_RD <= '0';
O_FREN <= "000101010000000000"; --FR set
-- EUC_ST <= "0110";
if(modo /= "11")then --result => ea
O_TMPRW <= "00"; --no writing
O_BUSCS <= A2B; --out data ALU => BIU
O_WR <= '1';
else --result => ea
O_GRRW <= '1'; --write GR
O_BUSCS <= A2G; --ALU => GR
O_TMPRW <= "00"; --read tmpREG1
O_GRSEL <= bw & rm; --set GR
end if;
--MUL------------------------------------------------------------------
--EA calculate
when MUL1 =>
O_MOD <= I_BDATA(7 downto 6); --output mod
modov := I_BDATA(7 downto 6); --save mod
O_RM <= I_BDATA(2 downto 0); --output r/m
rmv := I_BDATA(2 downto 0); --save r/m
O_MULHL <= '1'; --MUL out(low 8bit)
O_ALUCS <= KA; --ALU => ADD
mul_cv := "0000"; --shift count clear
if(I_BDATA(7 downto 6)= "11")then --register*register
O_GRRW <= '0'; --read GR
O_BUSCS <= G2T2; --GR => tmpREG2(reg2)
O_TMPRW <= "10"; --write tmpREG1
O_GRSEL <= bw & I_BDATA(2 downto 0); --set GR
else --memory=+register
O_EA <= '1'; --calculate EA
end if;
-- EUC_ST <= "0001";
--MUL reg*reg
when MUL2rr =>
O_GRRW <= '0'; --read GR
O_BUSCS <= G2T2; --tmpREG2 <= GR
O_TMPRW <= "10"; --write tmpREG2(divreg)
O_MULCS <= "01"; --tmp2in=>div_reg
O_GRSEL <= bw & "000"; --set GR(AX,AL)
O_ALUCS <= JOU; --ALU=>MUL
-- EUC_ST <= "0010";
--MUL mem*reg
when MUL2mr =>
O_RD <= '1'; --read memory data
O_EA <= '0';
O_BUSCS <= B2T2; --memory => tmpREG2(reg2)
O_ALUCS <= JOU; --ALU=>MUL
O_TMPRW <= "10"; --write tmpREG1
-- EUC_ST <= "0010";
when MUL2mr2 =>
O_RD <= '0';
O_TMPRW <= "10"; --write tmpREG2(divreg)
O_MULCS <="01"; --tmp2in=>div_reg
O_GRSEL <= bw & "000"; --set GR(AX,AL)
O_BUSCS <= G2T2; --tmpREG2 <= GR
-- EUC_ST <= "0011";
--loop for addition----
--addition ,when check bit of multiplier factor is '1'
when MULlp1 =>
if(I_LSBTR2 = '1')then --
O_TMPRW <= "01"; --
O_BUSCS <= A2T1; --
O_MULCS <= "10"; --tmp1in=>plus,tmp2in=>div
else --
O_TMPRW <= "00"; --
O_BUSCS <= "00000"; --can't use bus
O_MULCS <= "00"; --tmp1in=>plus,tmp2in=>div
end if;
O_MULHL <= '1'; --
mul_cv := mul_c + "0001"; --shift count
-- EUC_ST <= "0100";
--carry set
when MULlp2 =>
O_TMPRW <= "01"; --write reg1
O_BUSCS <= A2T1; --
O_MULHL <= '0'; --
O_MULCS <= "00"; --
-- EUC_ST <= "0101";
--1bit shift(reg1&plusreg®2)
when MULlp3 =>
O_TMPRW <= "00"; --read only
O_MULCS <= "11"; --reg1&plusreg®2 shift
O_BUSCS <= "00000"; --can't use bus
-- EUC_ST <= "0110";
when MULlp4 =>
O_TMPRW <= "00"; --
O_MULCS <= "00"; --
O_BUSCS <= "00000"; --
-- EUC_ST <= "1111"; --wait state-------(loop end)---
--MUL write
when MUL3 =>
O_GRRW <= '1'; --write GR
O_BUSCS <= T12G; --plus_reg => GR
O_REG3 <= '1'; --use plus_reg
O_TMPRW <= "00"; --read tmpREG1
O_FREN <= "000101010101010100"; --FR set(OF,CF)
O_GRSEL <= "1010"; --set GR(DX)
-- EUC_ST <= "0111";
when MUL4 => O_GRRW <= '1'; --write GR
if(bw = '0')then
O_BUSCS <= A2G; --ADJUST
O_ADJUST <= "11";
O_REG3 <= '1';
else
O_BUSCS <= T22G; --plus_reg => GR
O_REG3 <= '1';
end if;
O_TMPRW <= "00"; --read tmpREG1
O_FREN <= "000101010101010100"; --FR set
O_GRSEL <= "1000"; --set GR(AX)
-- EUC_ST <= "1000";
--IMUL---------------------------------------------------------------------
--EA calculate
when IMUL1 =>
O_MOD <= I_BDATA(7 downto 6); --output mod
modov := I_BDATA(7 downto 6); --save mod
O_RM <= I_BDATA(2 downto 0); --output r/m
rmv := I_BDATA(2 downto 0); --save r/m
signv := '0'; --clear
O_MULHL <= '1'; --MUL out(low 8bit)
O_ALUCS <= KA; --ALU => ADD
mul_cv := "0000"; --shift count clear
O_MULCS <= "00";
if(I_BDATA(7 downto 6)= "11")then --register*register
O_GRRW <= '0'; --read GR
O_BUSCS <= G2T1; --GR => tmpREG1
O_TMPRW <= "01"; --write tmpREG1
O_GRSEL <= bw & I_BDATA(2 downto 0); --set GR
else --memory=+register
O_EA <= '1'; --calculate EA
end if;
-- EUC_ST <= "0001";
when IMUL1w =>
null; --wait
when IMUL1c =>
O_GRRW <= '0'; --read GR
O_ALUCS <= "1111"; --negate
if(bw = '0')then
if(I_BSIGNTR1 = '1')then
signv := '1';
O_BUSCS <= A2T2; --tmpREG2 <= GR
else
O_BUSCS <= T12T2; --tmp1=>tmp2(reg2)
end if;
else
if(I_SIGNTR1 = '1')then
signv := '1';
O_BUSCS <= A2T2; --tmpREG2 <= GR
else
O_BUSCS <= T12T2; --tmp1=>tmp2(reg2)
end if;
end if;
O_TMPRW <= "10"; --write tmpREG2
-- EUC_ST <= "0010";
--MUL reg*reg
when IMUL2r =>
O_GRRW <= '0'; --read GR
O_BUSCS <= G2T1; --tmpREG2 <= GR
O_TMPRW <= "01"; --write tmpREG2
O_GRSEL <= bw & "000"; --set GR(AX,AL)
-- EUC_ST <= "0011";
when IMUL2rw =>
null; --wait
when IMUL2rc =>
O_GRRW <= '0'; --read GR
O_TMPRW <= "10"; --write tmpREG2(divreg)
O_MULCS <= "01"; --use divreg
if(bw = '0')then
if(I_BSIGNTR1 = '1')then
signv := not sign;
O_BUSCS <= A2T2; --tmpREG2 <= ALU
else
O_BUSCS <= T12T2; --tmp1=>tmp2(divreg)
end if;
else
if(I_SIGNTR1 = '1')then
signv := not sign;
O_BUSCS <= A2T2; --tmpREG2 <= ALU
else
O_BUSCS <= T12T2; --tmp1=>tmp2(divreg)
end if;
end if;
-- EUC_ST <= "0100";
--MUL mem*reg
when IMUL2m =>
O_RD <= '1'; --read memory data
O_EA <= '0';
O_BUSCS <= B2T1; --memory => tmpREG1
O_ALUCS <= JOU; --ALU=>MUL
O_TMPRW <= "01"; --write tmpREG1
-- EUC_ST <= "0011";
when IMUL2mw =>
null; --wait
when IMUL2mc =>
O_GRRW <= '0'; --read GR
O_ALUCS <= "1111"; --negate
if(bw = '0')then
if(I_BSIGNTR1 = '1')then
signv := '1';
O_BUSCS <= A2T2; --tmpREG2 <= GR
else
O_BUSCS <= T12T2; --tmp1=>tmp2
end if;
else
if(I_SIGNTR1 = '1')then
signv := '1';
O_BUSCS <= A2T2; --tmpREG2 <= GR
else
O_BUSCS <= T12T2; --tmp1=>tmp2
end if;
end if;
O_TMPRW <= "10"; --write tmpREG2
-- EUC_ST <= "0100";
when IMUL2m2 =>
O_RD <= '0';
O_TMPRW <= "01"; --write tmpREG1
O_GRSEL <= bw & "000"; --set GR(AX,AL)
O_BUSCS <= G2T1; --tmpREG1 <= GR
-- EUC_ST <= "0101";
when IMUL2m2w =>
null; --wait
when IMUL2m2c =>
O_GRRW <= '0'; --read GR
O_TMPRW <= "10"; --write tmp2(divreg)
O_MULCS <= "01"; --use divreg
if(bw = '0')then
if(I_BSIGNTR1 = '1')then
signv := not sign;
O_BUSCS <= A2T2; --tmpREG2 <= ALU
else
O_BUSCS <= T12T2; --tmp1=>tmp2(divreg)
end if;
else
if(I_SIGNTR1 = '1')then
signv := not sign;
O_BUSCS <= A2T2; --tmpREG2 <= ALU
else
O_BUSCS <= T12T2; --tmp1=>tmp2(divreg)
end if;
end if;
-- EUC_ST <= "0110";
--loop for addition----
--addition ,when check bit of multiplier factor is '1'
when IMULlp1 =>
if(I_LSBTR2 = '1')then
O_TMPRW <= "01"; --
O_BUSCS <= A2T1; --
O_MULCS <= "10"; --tmp1in=>plus,tmp2in=>div
else --
O_TMPRW <= "00"; --
O_BUSCS <= "00000"; --can't use bus
O_MULCS <= "00"; --tmp1in=>plus,tmp2in=>div
end if; --
O_MULHL <= '1'; --
O_ALUCS <= JOU; --
mul_cv := mul_c + "0001"; --shift count
-- EUC_ST <= "0100";
--carry set
when IMULlp2 =>
O_TMPRW <= "01"; --write reg1
O_BUSCS <= A2T1; --
O_MULHL <= '0'; --
O_MULCS <= "00"; --
-- EUC_ST <= "0101"; --
--1bit shift(reg1&plusreg®2)
when IMULlp3 =>
O_TMPRW <= "00"; --read only
O_MULCS <= "11"; --reg1&plusreg®2 shift-
O_BUSCS <= "00000"; --c⌨️ 快捷键说明
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