📄 ripupeuc2.vhd
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O_BUSCS <= G2T2; --tmpREG2 <= GR
O_TMPRW <= "10"; --write tmpREG2
O_GRSEL <= bw & reg; --set GR
-- EUC_ST <= "0101";
--ADD mem+reg
when ADD3mr =>
O_RD <= '1'; --read memory data
O_EA <= '0';
O_BUSCS <= B2T1; --memory => tmpREG1
O_TMPRW <= "01"; --write tmpREG1
-- EUC_ST <= "0110";
when ADD3mr2 =>
O_RD <= '0';
O_TMPRW <= "10"; --write tmpREG2
O_GRSEL <= bw & reg; --set GR
O_BUSCS <= G2T2; --tmpREG2 <= GR
-- euc_st <= "0111";
--ADD write
when ADD4 =>
O_RD <= '0';
-- EUC_ST <= "1000";
if(op(7 downto 2) = ADC)then --for ADC
O_USECARRY <= '1';
end if;
if(modo /= "11")then
O_TMPRW <= "00"; --no writing
if(d='1')then --result => reg
O_GRRW <= '1'; --write GR
O_GRSEL <= bw & reg; --set GR
O_BUSCS <= A2G; --out data ALU => GR
O_FREN <= "000101010000000000"; --FR set
else --result => ea
O_BUSCS <= A2B; --out data ALU => BIU
O_WR <= '1';
end if;
else
O_GRRW <= '1'; --write GR
O_BUSCS <= A2G; --ALU => GR
O_TMPRW <= "00"; --read tmpREG1
O_FREN <= "000101010000000000"; --FR set
if(d='1')then --result => reg
O_GRSEL <= bw & reg; --set GR
else --result => ea
O_GRSEL <= bw & rm; --set GR
end if;
end if;
when ADD5 =>
O_FREN <= "000101010000000000"; --FR set
-- EUC_ST <= "1001";
--immediate to register/memory(ADD,ADC)
when ADDie3 =>
if(modo /= "11")then
O_RD <= '1';
end if;
O_EA <= '0';
O_BUSCS <= B2T1; --memory => tmpREG1
O_TMPRW <= "01"; --write tmpREG1
-- EUC_ST <= "0101";
--read immediate data
when ADDie4 =>
O_BUSCS <= B2T2; --tmpREG2 <= data
O_TMPRW <= "10"; --write tmpREG2
O_RD <= '0';
-- EUC_ST <= "0110";
when ADDie_c =>
null; --wait state for check empty
when ADDie4_2 => null;
-- EUC_ST <= "0111";
when ADDie4_3 =>
-- EUC_ST <= "1000";
if(d = '0' and bw = '1')then
O_D16HL <= '1'; --16bit data
elsif(d = '1' and bw = '1')then
O_SE <= '1'; --sign extension(8bit=>16bit)
else
null;
end if;
-- write
when ADDie5 =>
O_RD <= '0';
-- EUC_ST <= "1001";
if(reg = "010")then --for ADCie
O_USECARRY <= '1';
end if;
if(modo /= "11")then --result => ea
O_TMPRW <= "00"; --no writing
O_BUSCS <= A2B; --out data ALU => BIU
O_WR <= '1';
else --result => ea
O_GRRW <= '1'; --write GR
O_BUSCS <= A2G; --ALU => GR
O_TMPRW <= "00"; --read tmpREG1
O_GRSEL <= bw & rm; --set GR
O_FREN <= "000101010000000000"; --FR set
end if;
when ADDie6 =>
O_FREN <= "000101010000000000"; --FR set
-- EUC_ST <= "1010";
--immediate to accumulator(ADDia,ADCia)
--input op code
when ADDia1 => null;
--TTMPOUT <= I_BDATA(7 downto 0);
-- EUC_ST <= "0011";
--calculate EA
when ADDia2 =>
--TTMPOUT <= I_BDATA(7 downto 0);
-- EUC_ST <= "0100";
O_ALUCS <= KA; --ALU => ADD
O_GRRW <= '0'; --read GR
O_BUSCS <= G2T1; --GR => tmpREG1
O_TMPRW <= "01"; --write tmpREG1
O_GRSEL <= bw & "000"; --set GR
-- Top1 <= I_BDATA;
--read immediate data
when ADDia3 => null;
--TTMPOUT <= I_BDATA(7 downto 0);
-- O_BUSCS <= B2T2; --tmpREG2 <= data
-- O_TMPRW <= "10"; --write tmpREG2
-- O_RD <= '0';
-- EUC_ST <= "0101"; --wait state for check empty
when ADDia_c =>
-- EUC_ST <= "0110";
--TTMPOUT <= I_BDATA(7 downto 0);
tmpv := I_BDATA(7 downto 0);
when ADDia4 => null;
--O_ALUCS <= KA;
-- EUC_ST <= "0111";
--TTMPOUT <= I_BDATA;
--tmpv := I_BDATA(7 downto 0);
when ADDia5 =>
--TTMPOUT <= I_BDATA(7 downto 0);
--TTMPOUT <=tmp;
O_DATA <= I_BDATA(7 downto 0)&tmp;
--if(op(0) = '1')then
-- O_D16HL <= '1'; --16bit data
--end if;
if(op(7 downto 1) = ADCia)then --for ADCia
O_USECARRY <= '1';
end if;
O_2EU <= '1';
O_BUSCS <= B2T2;
O_ALUCS <= KA;
O_TMPRW <= "10";
O_RD <= '0';
--- EUC_ST <= "1000";
-- write
when ADDia6 =>
O_ALUCS <= KA;
--TTMPOUT <= I_BDATA(7 downto 0);
O_RD <= '0';
O_FREN <= "000101010000000000"; --FR set
-- EUC_ST <= "1001";
if(op(7 downto 1) = ADCia)then --for ADCia
O_USECARRY <= '1';
end if;
O_GRRW <= '1'; --write GR
O_BUSCS <= A2G; --ALU => GR
O_TMPRW <= "00"; --read tmpREG1
O_GRSEL <= bw & "000"; --set AX(AL)
--INC---------------------------------------------------------------------
--INC EA+1----
--input op code
when INC1 => null;
-- EUC_ST <= "0011";
--calculate EA
when INC2 =>
O_MOD <= I_BDATA(7 downto 6); --output mod
modov := I_BDATA(7 downto 6); --save mod
regv := I_BDATA(5 downto 3); --save reg
O_RM <= I_BDATA(2 downto 0); --output r/m
rmv := I_BDATA(2 downto 0); --save r/m
-- EUC_ST <= "0100";
if(I_BDATA(7 downto 6)= "11")then --register+1
O_GRRW <= '0'; --read GR
O_BUSCS <= G2T1; --GR => tmpREG1
O_TMPRW <= "11"; --write tmpREG1
O_1SETTR2 <= '1'; --set 1 to tmp2
O_GRSEL <= bw & I_BDATA(2 downto 0); --set GR
if(I_BDATA(5 downto 3) = "001")then
O_ALUCS <= GEN; --ALU => SUB (when DEC)
else
O_ALUCS <= KA; --ALU => ADD
end if;
else --memory+1
O_EA <= '1'; --calculate EA
O_ALUCS <= KA; --ALU => ADD
end if;
when INC3 =>
if(modo /= "11")then
O_RD <= '1';
end if;
O_EA <= '0';
O_BUSCS <= B2T1; --memory => tmpREG1
O_TMPRW <= "11"; --write tmpREG1,tmpREG2
O_1SETTR2 <= '1'; --set 1 to tmp2
-- EUC_ST <= "0101";
if(I_BDATA(5 downto 3) = "001")then
O_ALUCS <= GEN; --ALU => ADD(when DEC)
end if;
-- write
when INC4 =>
O_RD <= '0';
O_FREN <= "000101010000000001"; --FR set
O_1SETTR2 <= '0';
-- EUC_ST <= "0110";
if(modo /= "11")then --result => ea
O_TMPRW <= "00"; --no writing
O_BUSCS <= A2B; --out data ALU => BIU
O_WR <= '1';
else --result => ea
O_GRRW <= '1'; --write GR
O_BUSCS <= A2G; --ALU => GR
O_TMPRW <= "00"; --read tmpREG1
O_GRSEL <= bw & rm; --set GR
end if;
---INC Register+1----
-- when INCr1 =>
-- O_BW <= '1'; --output byte or word
-- O_GRRW <= '0'; --read GR
-- O_BUSCS <= G2T1; --GR => tmpREG1
-- O_TMPRW <= "11"; --write tmpREG1
-- O_1SETTR2 <= '1'; --set 1 to tmp2
-- O_GRSEL <= '1' & I_BDATA(2 downto 0); --set GR
-- -- EUC_ST <= "0011";
-- when INCr2 =>
-- if(I_BDATA(7 downto 3) = DECreg)then
-- O_ALUCS <= GEN; --ALU => SUB
-- else
-- O_ALUCS <= KA; --ALU => ADD
-- end if;
-- O_BUSCS <= A2G; --ALU => GR
-- O_FREN <= "000101010000000000"; --FR set
-- O_GRSEL <= '1' & I_BDATA(2 downto 0);
-- O_GRRW <= '1';
-- EUC_ST <= "0100";
--AAA (AAS)-------------------------------------------------------------------
when AAA1 =>
O_BUSCS <= G2T1; --GR => tmpREG1
O_GRRW <= '0'; --read GR
O_TMPRW <= "01"; --write tmpREG1
O_GRSEL <= "1000"; --read AX
if(op = AAS)then
O_ALUCS <= GEN; --ALU => SUB
else
O_ALUCS <= KA; --ALU => ADD
end if;
-- EUC_ST <= "0011";
when AAA2 =>
O_BUSCS <= A2G; --ALU => GR
O_GRRW <= '1'; --write GR
O_TMPRW <= "00"; --read tmpREG1
O_GRSEL <= "1000"; --write AX
O_ADJUST <= "01"; --ASCII adjust
O_FREN <= "010101010101000100"; --af.cf set
-- EUC_ST <= "0100";
--DAA-------------------------------------------------------------------
when DAA1 =>
O_BUSCS <= G2T1; --GR => tmpREG1
O_GRRW <= '0'; --read GR
O_TMPRW <= "01"; --write tmpREG1
O_GRSEL <= "1000"; --read AX
if(op = DAS)then
O_ALUCS <= GEN; --ALU => SUB
else
O_ALUCS <= KA; --ALU => ADD
end if;
O_BW <= '0';
-- EUC_ST <= "0011";
when DAA2 =>
O_BUSCS <= A2G; --ALU => GR
O_GRRW <= '1'; --write GR
O_TMPRW <= "00"; --read tmpREG1
O_GRSEL <= "0000"; --write AX
O_ADJUST <= "10"; --ASCII adjust
O_FREN <= "010101010000000000"; --sf,zf,af,pf.cf set
-- EUC_ST <= "0100";
--SUB--------------------------------------------------------------------
--register/memmory with register to either
--input OP code
when SUB1=> null;
-- EUC_ST <= "0011";
--EA calculate
when SUB2 =>
O_MOD <= I_BDATA(7 downto 6); --output mod
modov := I_BDATA(7 downto 6); --save mod
regv := I_BDATA(5 downto 3); --save reg
O_RM <= I_BDATA(2 downto 0); --output r/m
rmv := I_BDATA(2 downto 0); --save r/m
-- EUC_ST <= "0100";
O_ALUCS <= GEN; --ALU => ADD
if(I_BDATA(7 downto 6)= "11")then --register+register
O_GRRW <= '0'; --read GR
O_GRSEL <= bw & I_BDATA(2 downto 0); --set GR
if(d = '1')then
O_BUSCS <= G2T2; --GR => tmpREG2
O_TMPRW <= "10"; --write tmpREG2
else
O_BUSCS <= G2T1; --GR => tmpREG1
O_TMPRW <= "01"; --write tmpREG1
end if;
else --memory=+register
O_EA <= '1'; --calculate EA
end if;
--SUB reg-reg
when SUB3rr =>
O_ALUCS <= GEN; --ALU => SUB
O_GRRW <= '0'; --read GR
if(d = '1')then
O_BUSCS <= G2T1; --tmpREG1 <= GR
O_TMPRW <= "01"; --write tmpREG1
else
O_BUSCS <= G2T2; --tmpREG2 <= GR
O_TMPRW <= "10"; --write tmpREG2
end if;
O_GRSEL <= bw & reg; --set GR
-- EUC_ST <= "0101";
--SUB mem,reg
when SUB3mr =>
O_ALUCS <= GEN; --ALU_=> SUB
O_RD <= '1'; --read memory data
O_EA <= '0';
if(d = '1')then
O_BUSCS <= B2T2; --memory => tmpREG2
O_TMPRW <= "10"; --write tmpREG2
else
O_BUSCS <= B2T1; --memory => tmpREG1
O_TMPRW <= "01"; --write tmpREG1
end if;
-- EUC_ST <= "0110";
when SUB3mr2 =>
O_RD <= '0';
O_GRSEL <= bw & reg; --set GR
if(d = '1')then
O_TMPRW <= "01"; --write tmpREG1
O_BUSCS <= G2T1; --tmpREG1 <= GR
else
O_TMPRW <= "10"; --write tmpREG2
O_BUSCS <= G2T2; --tmpREG2 <= GR
end if;
-- EUC_ST <= "0111";
--SUB write
-- when SUB4 =>
-- O_RD <= '0';
-- -- EUC_ST <= "1000";
-- O_ALUCS <= GEN; --ALU => SUB
-- if(op(7 downto 2) = SBB)then --for SBB
-- O_USECARRY <= '1';
-- end if;
--
-- if(op(7 downto 2) /= CMP)then
-- if(modo /= "11")then
-- O_TMPRW <= "00"; --no writing
-- if(d='1')then --result => reg
-- O_GRRW <= '1'; --write GR
-- O_GRSEL <= bw & reg; --set GR
-- O_BUSCS <= A2G; --out data ALU => GR
-- O_FREN <= "000101010000000000"; --FR set
-- else --result => ea
-- O_BUSCS <= A2B; --out data ALU => BIU
-- O_WR <= '1';
-- end if;
-- else
-- O_GRRW <= '1'; --write GR
-- O_BUSCS <= A2G; --ALU => GR
-- O_TMPRW <= "00"; --read tmpREG1
-- O_FREN <= "000101010000000000"; --FR set
-- if(d='1')then --result => reg
-- O_GRSEL <= bw & reg; --set GR
-- else --result => ea
-- O_GRSEL <= bw & rm; --set GR
-- end if;
-- end if;
-- else
-- O_FREN <= "000101010000000000"; --FR set
-- end if;
-- when SUB5 =>
-- O_FREN <= "000101010000000000"; --FR set
-- -- EUC_ST <= "1001";
--immediate to register/memory(ADD,ADC)
-- when SUBie3 =>
-- if(modo /= "11")then
-- O_RD <= '1';
-- end if;
-- O_EA <= '0';
-- O_BUSCS <= B2T1; --memory => tmpREG1
-- O_TMPRW <= "01"; --write tmpREG1
-- -- EUC_ST <= "0101";
--read immediate data
-- when SUBie4 =>
-- O_BUSCS <= B2T2; --tmpREG2 <= data
-- O_TMPRW <= "10"; --write tmpREG2
-- O_RD <= '0';
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