📄 ripupeuc2.vhd
字号:
plusv := "001"; -- +1
--read (SP)
when POPsr2 =>
O_RD <= '1';
O_CSR <= '1'; --CSEG control by EUC
O_SRSEL <= "10"; --set CSEG to SS
-- EUC_ST <= "0100";
--end read stack data,write to Register
when POPsr3 =>
O_CSR <= '1';
O_SRSEL <= modo; --seg CSEG
O_MDTF <= '1'; --'1' => REGDT <= MEMORY DATA
O_WRSR <= '1'; --write to Segment Reg
-- EUC_ST <= "0101";
--XCHG------------------------------------------------------------------------
when XCHGm1 =>
-- EUC_ST <= "0011";
plusv := "010"; -- +2
when XCHGm2 =>
O_MOD <= I_BDATA(7 downto 6); --output mod
modov := I_BDATA(7 downto 6);
O_RM <= I_BDATA(2 downto 0); --output r/m
rmv := I_BDATA(2 downto 0); --ratch rm
-- EUC_ST <= "0100";
O_ALUCS <= KA; --ALU => ADD
O_BUSCS <= G2T1; --GR => tmpREG1
if(I_BDATA(7 downto 6)= "11")then --register => register
O_GRSEL <= bw & I_BDATA(2 downto 0); --r/m set GR
regv := I_BDATA(2 downto 0);
O_TMPRW <= "01"; --write tmpREG1
else --memory=>register
O_EA <= '1'; --calculate EA
O_GRSEL <= bw & I_BDATA(5 downto 3); --set GR
regv := I_BDATA(5 downto 3);
end if;
--wait calculate EA
when XCHGm3 =>
-- EUC_ST <= "0101";
O_EA <= '1';
--register => register
when XCHGrr3 =>
O_GRSEL <= bw & I_BDATA(5 downto 3); --set GR
regv := I_BDATA(5 downto 3);
O_BUSCS <= G2T2; --GR => tmpREG2
O_TMPRW <= "10"; --write tmpREG2
-- EUC_ST <= "1001";
when XCHGrr4 =>
O_GRRW <= '1'; --write GR
O_BUSCS <= T12G; --tmpREG1 => GR
-- EUC_ST <= "1010";
when XCHGrr5 =>
O_GRRW <= '1'; --write GR
O_GRSEL <= bw & I_BDATA(2 downto 0); --r/m set GR
regv := I_BDATA(2 downto 0);
O_BUSCS <= T22G; --tmpREG2 => GR
-- EUC_ST <= "1011";
--memory=>register
--end caluculate EA
when XCHGmr3 =>
O_RD <= '1'; --read mem
O_BUSCS <= G2T2; --GR => tmpREG2
O_TMPRW <= "10"; --write tmpREG2
-- EUC_ST <= "0110";
--end read mem data,write to GR
when XCHGmr4 =>
O_GRRW <= '1'; --write GR
O_BUSCS <= B2G; --data BIU => GR
-- EUC_ST <= "0111";
--write to memory
when XCHGmr5 =>
O_WR <= '1';
O_BUSCS <= T22B; --tmpREG2 => BIU
O_TMPRW <= "00"; --read tmpREG12
-- EUC_ST <= "1000";
--REG <=> AX
--read REG data to tmpREG1
when XCHGax1 =>
O_GRSEL <= '1' & I_BDATA(2 downto 0); --set GR
regv := I_BDATA(2 downto 0);
O_BUSCS <= G2T1; --GR => tmpREG1
O_TMPRW <= "01"; --write tmpREG1
-- EUC_ST <= "1100";
modov := "00";
plusv := "001"; -- +1
--read AX to tmpREG2
when XCHGax2 =>
O_GRSEL <= "1000"; --set GR AX
O_BUSCS <= G2T2; --GR => tmpREG1
O_TMPRW <= "10"; --write tmpREG2
-- EUC_ST <= "1101";
--write tmpREG2 to REG
when XCHGax3 =>
O_GRRW <= '1'; --write GR
O_BUSCS <= T22G; --tmpREG2 => GR
O_GRSEL <= '1' & I_BDATA(2 downto 0); --set GR
-- EUC_ST <= "1110";
--write tmpREG1 to AX
when XCHGax4 =>
O_GRRW <= '1'; --write GR
O_GRSEL <= "1000"; --set GR AX
O_BUSCS <= T12G; --tmpREG1 => GR
-- EUC_ST <= "1111";
--IN ----------------------------------------------------------------------
when INN1 =>
--TTMPOUT <=I_BDATA;
O_IO <= '1'; --access I/O device
-- EUC_ST <= "0011";
modov := "00";
plusv := "010"; -- +2
--address out
when INN2 =>
--TTMPOUT <=I_BDATA;
O_RD <= '1';
O_IO <= '1'; --access I/O device
O_OADR <= "00000000"&I_BDATA; --output address
-- EUC_ST <= "0100";
--write to GR
when INN3 =>
--TTMPOUT <=I_BDATA;
O_GRRW <= '1'; --write GR
O_BUSCS <= B2G; --BIU => GR
-- EUC_ST <= "0101";
if(bw='1')then
O_GRSEL <= "1000"; --set GR AX
else
O_GRSEL <= "0000"; --set GR AL
end if;
-- IN dx ---------------------------------------
when INdx1 =>
--TTMPOUT <=I_BDATA;
O_GRSEL <= "1010"; --set GR DX
regv := "010";
O_BUSCS <= G2B; --GR => BIU
-- EUC_ST <= "0110";
modov := "00";
plusv := "001"; -- +1
when INdx2 =>
--TTMPOUT <=I_BDATA;
O_IO <= '1'; --access I/O device
O_RD <= '1';
O_OADR <= I_DATA; --output address
-- EUC_ST <= "0111";
--OUT -----------------------------------------------------------------------
when OUTT1 =>
--O_IO <= '1'; --access I/O device
-- EUC_ST <= "0011";
modov := "00";
plusv := "010"; -- +2
--address out,data out
when OUTT2 => --output byte or word
O_WR <= '1'; --write
O_IO <= '1'; --access I/O device
O_OADR <= "00000000"&I_BDATA; --output port address
O_BUSCS <= G2B; --GR => BIU
-- EUC_ST <= "0100";
if(bw='1')then
O_GRSEL <= "1000"; --set GR AX
else
O_GRSEL <= "0000"; --set GR AL
end if;
--out dx----------------------------------------
when OUTdx1 =>
O_GRSEL <= "1010"; --set GR DX
regv := "010";
O_BUSCS <= G2B; --GR => BIU
-- EUC_ST <= "0101";
modov := "00";
plusv := "001"; -- +1
--ratch DX
when OUTdx2 =>
dxxv := I_DATA; --ratch DX data
-- EUC_ST <= "0110";
--address out,data out
when OUTdx3 =>
O_IO <= '1'; --access I/O device
O_WR <= '1'; --write
O_OADR <= dxx; --output port address
O_BUSCS <= G2B; --GR => BIU
-- EUC_ST <= "0111";
if(bw='1')then
O_GRSEL <= "1000"; --set GR AX
else
O_GRSEL <= "0000"; --set GR AL
end if;
-- XLAT ---------------------------------------------------------------------------
--BX => tmp1
when XLAT1 =>
O_GRSEL <= "1011"; --set GR BX
O_BUSCS <= G2T1; --GR => tmpREG1
O_TMPRW <= "01"; --write tmpREG1
O_ALUCS <= KA; --ALU => ADD
-- EUC_ST <= "0011";
modov := "00";
plusv := "001"; -- +1
--AL => tmp2
when XLAT2 =>
O_GRSEL <= "0000"; --set GR AL
O_BUSCS <= G2T2; --GR => tmpREG2
O_TMPRW <= "10"; --write tmpREG2
-- EUC_ST <= "0100";
--BX+AL => IS
when XLAT3 =>
O_BUSCS <= A2B; --ALU => BIU
O_WRIR <= '1'; --write IR
O_CSR <= '1'; --CSEG control by EUC
O_SRSEL <= "10"; --set CSEG to SS
-- EUC_ST <= "0101";
--read memory data
when XLAT4 =>
O_RD <= '1'; --read memory
-- EUC_ST <= "0110";
--end read memory,write to AL
when XLAT5 =>
O_GRRW <= '1'; --write GR
O_GRSEL <= "0000"; --set GR AL
O_BUSCS <= B2G; --data BIU => GR
-- EUC_ST <= "0111";
--LEA -----------------------------------------------------------------
when LEA1 =>
-- EUC_ST <= "0011";
plusv := "010"; -- +2
--caluculate EA
when LEA2 =>
O_MOD <= I_BDATA(7 downto 6); --output mod
modov := I_BDATA(7 downto 6);
O_RM <= I_BDATA(2 downto 0); --output r/m
rmv := I_BDATA(2 downto 0); --ratch rm
--output byte or word
O_GRSEL <= bw & I_BDATA(5 downto 3); --set GR
regv := I_BDATA(5 downto 3);
O_ALUCS <= KA; --ALU => ADD
O_EA <= '1'; --calculate EA
-- EUC_ST <= "0100";
--wait calculate EA
when LEA22 =>
-- EUC_ST <= "0101";
O_EA <= '1';
--end caluculate EA
when LEA3 =>
O_RDIR <= '1'; --read IR
O_GRRW <= '1'; --write GR
O_BUSCS <= B2G; --BIU =>GR
-- EUC_ST <= "0110";
--LDS ------------------------------------------------------------------
when LDSES1 =>
-- EUC_ST <= "0011";
plusv := "010"; -- +2
--caluculate EA
when LDSES2 =>
O_MOD <= I_BDATA(7 downto 6); --output mod
modov := I_BDATA(7 downto 6);
O_RM <= I_BDATA(2 downto 0); --output r/m
rmv := I_BDATA(2 downto 0); --ratch rm
O_GRSEL <= '1' & I_BDATA(5 downto 3); --set GR
regv := I_BDATA(5 downto 3);
O_BW <= '1'; --output byte or word
O_ALUCS <= KA; --ALU => ADD
O_EA <= '1'; --calculate EA
-- EUC_ST <= "0100";
--wait calculate EA
when LDSES22 =>
-- EUC_ST <= "0101";
O_EA <= '1';
--end caluculate EA,read memory data
when LDSES3 =>
O_RD <= '1';
-- EUC_ST <= "0110";
--write GR,read EA+2
when LDSES4 =>
O_GRRW <= '1'; --write GR
O_BUSCS <= B2G; --BIU =>GR
O_RD <= '1';
O_EAPLUS2 <= '1'; --EA+2
O_MDTF <= '1'; --Memory data to Segment Reg
-- EUC_ST <= "0111";
--end write GR,read memory
when LDSES5 =>
O_EAPLUS2 <= '1'; --EA+2
O_RD <= '1';
O_MDTF <= '1'; --Memory data to Segment Reg
-- EUC_ST <= "1000";
--end read EA+2 data, write DS
when LDS6 =>
O_WRSR <= '1'; --write to Segment Reg
O_CSR <= '1'; --set Segment Reg
O_SRSEL <= "11"; --set DS
O_MDTF <= '1'; --Memory data to Segment Reg
-- EUC_ST <= "1001";
--write ES
when LES6 =>
O_WRSR <= '1'; --write to Segment Reg
O_CSR <= '1'; --set Segment Reg
O_SRSEL <= "00"; --set ES
O_MDTF <= '1'; --Memory data to Segment Reg
-- EUC_ST <= "1010";
--------------------------------------------------------------------------ishimura
--LAHF -------------------------------------------------------------------
when LAHF1 =>
O_BW <= '1';
O_BUSCS <= F2G; --FR =>GR
O_GRSEL <= "0100"; --AH
O_GRRW <= '1'; --write
O_FREN <= "010101010101010101"; --FR mask(all)
--SAHF -------------------------------------------------------------------
when SAHF1 =>
O_BW <= '1'; --as byte data
O_BUSCS <= G2F; --GR =>FR
O_GRSEL <= "0100"; --AH
O_GRRW <= '0'; --read
O_FRSEL <= '1'; --store to FR
O_FREN <= "010101010000000000"; --CFR mask
---------------------------------------------------------------------------/ishimura
--PUSHF ------------------------------------------------------------------
--write SP to tmp1
when PUSHF1 =>
O_2SETTR2 <= '1'; --set 2 to tmpreg
O_GRSEL <= "1100"; --set SP(GR)
regv := "100";
O_BW <= '1';
O_BUSCS <= G2T1; --GR => tmpREG1
O_TMPRW <= "01"; --write tmpREG1
-- EUC_ST <= "0011";
modov := "00";
plusv := "001"; -- +1
--write(SP-2) to SP
when PUSHF2 =>
O_GRRW <= '1'; --write GR
O_ALUCS <= GEN; --ALU => SUB
O_BUSCS <= A2G; --ALU => GR
O_TMPRW <= "00";
-- EUC_ST <= "0100";
--write(SP-2) to IR
when PUSHF3 =>
O_GRSEL <= "1100"; --set SP(GR)
O_WRIR <= '1'; --write signal to IR
O_BUSCS <= G2B; --data GR => BIU
-- EUC_ST <= "0101";
--write stack
when PUSHF4 =>
O_WR <= '1';
O_CSR <= '1'; --CSEG control by EUC
O_SRSEL <= "10"; --set CSEG to SS
O_BUSCS <= F2B; --data FR => BIU
-- EUC_ST <= "0110";
--POPF -------------------------------------------------------------------
--SP write IR
when POPF1 =>
O_BW <= '1'; --output byte or word
O_GRSEL <= "1100"; --set SP(GR)
regv := "100";
O_WRIR <= '1'; --write signal to IR
O_BUSCS <= G2B; --data GR => BIU
-- EUC_ST <= "0011";
modov := "00";
plusv := "001"; -- +1
--read (SP)
when POPF2 =>
O_RD <= '1';
O_CSR <= '1'; --CSEG control by EUC
O_SRSEL <= "10"; --set CSEG to SS
-- EUC_ST <= "0100";
--end read stack data,write to Register
when POPF3 =>
O_BUSCS <= B2F; --data BIU => FR
O_FRSEL <= '1'; --to flag reg '1'=>BUS data '0'=>ALU data
O_FREN <= "000000000000000000"; -- write flag register
-- EUC_ST <= "0101";
-----------------------------------------------------------------------------------------------ishimura
--ADD ----------------------------------------------------------------------
--register/memmory with register to either
--input OP code
when ADD1=> null;
-- EUC_ST <= "0011";
--EA calculate
when ADD2 =>
O_MOD <= I_BDATA(7 downto 6); --output mod
modov := I_BDATA(7 downto 6); --save mod
regv := I_BDATA(5 downto 3); --save reg
O_RM <= I_BDATA(2 downto 0); --output r/m
rmv := I_BDATA(2 downto 0); --save r/m
--output byte or word
-- EUC_ST <= "0100";
O_ALUCS <= KA; --ALU => ADD
if(I_BDATA(7 downto 6)= "11")then --register+register
O_GRRW <= '0'; --read GR
O_BUSCS <= G2T1; --GR => tmpREG1
O_TMPRW <= "01"; --write tmpREG1
O_GRSEL <= bw & I_BDATA(2 downto 0); --set GR
else --memory=+register
O_EA <= '1'; --calculate EA
end if;
--ADD reg+reg
when ADD3rr =>
O_GRRW <= '0'; --read GR
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -