ripupeuc2.vhd

X8086的VHDL源码

--			EUC_ST <= "1100";
			if(bw = '1')then
				tmpv := I_BDATA(7 downto 0);
			else --write memory
				O_DATA <= "00000000" & I_BDATA(7 downto 0); --out bus immediate data
				O_2BIU <= '1'; --EUC data to BIU
                O_WR <= '1';
			end if;
--wait que data
		when MOVim6 => null;
--			EUC_ST <= "1101";	
--read end word data,write memory
		when MOVim7 => 
			O_DATA <= I_BDATA(7 downto 0) & tmp; --out bus immediate data
			O_2BIU <= '1'; --EUC data to BIU
			O_WR <= '1';
--			EUC_ST <= "1110";
--immediate to regisiter :::::::::::::::::::::::::::::::::::::::::::::
		when MOVireg1 => 
			regv := op(2 downto 0);
			modov := "00";
			if(op(3)='0')then
				plusv := "010"; -- +2
			else
				plusv := "011";       -- +3
			end if;
            tmpv := I_BDATA(7 downto 0);
--byte data	
		when MOViregb2 => 
			O_GRSEL <= op(3 downto 0); --set GR
			O_DATA <= "00000000" & I_BDATA(7 downto 0); --out bus immediate data
            O_2EU <= '1'; --out EUC data signal
			O_GRRW <= '1';  --write GR
			O_BUSCS <= B2G;   --data BIU => GR
--word data	
		when MOViregw2 => null;
			--O_GRSEL <= op(3 downto 0); --set GR    
		   	--O_DATA <= I_BDATA(7 downto 0) & tmp;  --out bus immediate data
		when MOViregw3 => 
		   	O_DATA <= I_BDATA(7 downto 0) & tmp;  --out bus immediate data
			O_GRSEL <= op(3 downto 0); --set GR
            O_2EU <= '1'; --EUC data to EU
			O_GRRW <= '1'; --write GR
            O_BUSCS <= B2G; --data BIU => GR
--Memory to Accumulator ::::::::::::::::::::::::::::::::::::::::::::::::::
		when MOVma1 => 
			regv := "000";
--			EUC_ST <= "0011";
			modov := "00";
			if(I_BDATA(0)='0')then
				plusv := "010"; -- +2
			else
				plusv := "011"; -- +3
			end if;
--write IR	
		when MOVmab2 =>                                
			O_WRIR <= '1';
			O_2SR <= '1'; --EUC DATA to Segment Registar 
			O_DATA <= "00000000" & I_BDATA(7 downto 0); --Immediate address 
--			EUC_ST <= "0100";
--word address
		when MOVmaw2 =>                                
			tmpv := I_BDATA(7 downto 0); --Immediate address 
--			EUC_ST <= "0100";
--write IR	
		when MOVmaw3 => 
			O_WRIR <= '1';
			O_2SR <= '1'; --EUC DATA to Segment Registar 
			O_DATA <= I_BDATA(7 downto 0) & tmp; --Immediate address 
--			EUC_ST <= "0101";
--read memory 
		when MOVma4 => 
			O_RD <= '1'; 
--			EUC_ST <= "0101";
--end read memory,write AL
		when MOVma5 => 
			O_GRRW <= '1'; --write GR
			O_BUSCS <= B2G; --data BIU => GR
--			EUC_ST <= "0110";
--Accumulator to Memory :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
		when MOVam1 => 
			regv := "000";
	--		EUC_ST <= "0011";
         	modov := "00";
			if(I_BDATA(0)='0')then
				plusv := "010"; -- +2
			else
				plusv := "011"; -- +3
			end if;
--write IR	
		when MOVamb2 =>                                
			O_WRIR <= '1';
			O_2SR <= '1'; --EUC DATA to Segment Registar 
			O_DATA <= "00000000" & I_BDATA(7 downto 0); --Immediate address 
	--		EUC_ST <= "0100";
--word address
		when MOVamw2 =>                                
			tmpv := I_BDATA(7 downto 0); --Immediate address 
	--		EUC_ST <= "0100";
--write IR						
		when MOVamw3 => 
			O_WRIR <= '1';
			O_2SR <= '1'; --EUC DATA to Segment Registar 
			O_DATA <= I_BDATA(7 downto 0) & tmp; --Immediate address 
--			EUC_ST <= "0101";
--write memory
		when MOVam4 => 
			O_BUSCS <= G2B; --out data GR => BIU
			O_WR <= '1';		                
--			EUC_ST <= "0110";
--Register/memory to Segment register :::::::::::::::::::::::::::::::::::::::
		when MOVrms1 => 
--			EUC_ST <= "0011";
			plusv := "010"; -- +2
		when MOVrms2 => 
			O_MOD <= I_BDATA(7 downto 6); --output mod		
	        modov := I_BDATA(7 downto 6); --ratch mod
			O_RM <= I_BDATA(2 downto 0); --output r/m
			rmv := I_BDATA(2 downto 0); --ratch rm
			O_SRSEL <= I_BDATA(4 downto 3); --set Segment Register
	--		EUC_ST <= "0100";
			O_ALUCS <= KA; --ALU => ADD
			regv := I_BDATA(2 downto 0);
			if(I_BDATA(7 downto 6)= "11")then -- => register			                
				O_GRSEL <= bw & I_BDATA(2 downto 0); --r/m set GR
				O_BUSCS <= G2B; --GR => BIU
			else                                   -- =>memory
			    O_EA <= '1'; --calculate EA
			end if;
--wait calculate EA
		when MOVrms3 => 
		--	EUC_ST <= "0101";
			O_EA <= '1';
--end caluculate EA,read memory data
		when MOVms3 => 
			O_RD <= '1';
	--		EUC_ST <= "0110";
--end read memory data,write to SR
		when MOVms4 => 
			O_MDTF <= '1'; --SR <= memory data
			O_WRSR <= '1'; --write to Segment Reg
			O_CSR <= '1'; --set Segment Reg
	--		EUC_ST <= "0111";
--write SR	
		when MOVrs3 => 
			O_WRSR <= '1'; --write to Segment Reg
            O_CSR <= '1'; --set Segment Reg
--			EUC_ST <= "1000";		
--Segment Register to Register/Memory :::::::::::::::::::::::::::::::::::::::
		when MOVsrm1 => 
	--		EUC_ST <= "0011";
			plusv := "010"; -- +2
--read SR	
		when MOVsrm2 => 
			O_MOD <= I_BDATA(7 downto 6); --output mod		
			modov := I_BDATA(7 downto 6); --ratch mod
			O_RM <= I_BDATA(2 downto 0); --output r/m
			rmv := I_BDATA(2 downto 0); --ratch rm
			O_SRSEL <= I_BDATA(4 downto 3); --set Segment Register
 	--		EUC_ST <= "0100";
			O_ALUCS <= KA; --ALU => ADD
			O_RDSR <= '1'; --read CSEG  
			O_CSR <= '1'; --CSEG control by EUC 
			regv := I_BDATA(2 downto 0);	
			if(I_BDATA(7 downto 6)= "11")then  -- => register			                
				O_GRSEL <= bw & I_BDATA(2 downto 0); --r/m set GR
				O_BUSCS <= B2G; --GR => BIU
			else                                    -- =>memory
			    O_EA <= '1'; --calculate EA
			end if;
--wait calculate EA
		when MOVsrm3 => 
--			EUC_ST <= "0101";
			O_EA <= '1';
--write GR	
		when MOVsr3 => 
			O_GRRW <= '1'; --write GR
  --          EUC_ST <= "0110";
--end caluculate EA,write SR data to tmp1
		when MOVsm3 => 
			O_BUSCS <= B2T1;
			O_TMPRW <= "01"; --write tmpREG1
--			EUC_ST <= "0111";
--write to memory
		when MOVsm4 => 
			O_BUSCS <= T12B;
			O_TMPRW <= "00"; --read tmpREG1
			O_WR <= '1';  
	--		EUC_ST <= "1000";
--PUSH-----------------------------------------------------------------------
--set tmp register ,calculate (SP-2)
		when SP2 => 
			O_2SETTR2 <= '1'; --set 2 to tmpreg
			O_GRSEL <= "1100";     
			regv := "100"; --set SP(GR)
            O_BW <= '1';	
			O_BUSCS <= G2T1; --GR => tmpREG1
			O_TMPRW <= "01"; --write tmpREG1                          
	--		EUC_ST <= "0011";
--write(SP-2) to SP
		when SPw => 
			O_GRSEL <= "1100";
			O_GRRW <= '1'; --write GR
			O_BUSCS <= A2G; --ALU => GR 
			O_ALUCS <= GEN; --ALU => SUB
			O_TMPRW <= "00";
	--		EUC_ST <= "0100";
--MEM => stack --------------------------------------------
--calculate EA
		when PUSHms1 => 
			O_MOD <= I_BDATA(7 downto 6); --output mod
			modov := I_BDATA(7 downto 6); --ratch mod
			O_RM <= I_BDATA(2 downto 0); --output r/m
			rmv := I_BDATA(2 downto 0); --ratch r/m
			O_BW <= '1'; --word								 
	--		EUC_ST <= "0101";
			O_ALUCS <= KA; --ALU => ADD
			plusv := "010"; -- +2
			if(I_BDATA(7 downto 6)="11")then --register mode
				O_EA <= '0';
			else
				O_EA <= '1'; --calculate EA
			end if;
--wait calculate EA
		when PUSHms11 => 
	--		EUC_ST <= "0101";						  				  							
			O_EA <= '1';
--end calculate EA
		when PUSHms2 => 
			O_RD <= '1'; --read MEM
	--		EUC_ST <= "0110";               
--end read mem data
		when PUSHms3 =>
			O_BUSCS <= B2T2; --data BIU => tmpREG2
			O_TMPRW <= "10"; --write tmpREG2
	--		EUC_ST <= "0111";
--write (SP) to IR
		when PUSHms4 => 
			O_GRSEL <= "1100"; --set SP(GR)
			O_WRIR <= '1'; --write signal to IR
			O_BUSCS <= G2B; --data GR => BIU
			O_TMPRW <= "00";         
	--		EUC_ST <= "1000";
--write stack
		when PUSHms5 => 
			O_WR <= '1';
			O_CSR <= '1'; --CSEG control by EUC
			O_SRSEL <= "10"; --set CSEG to SS
	--		EUC_ST <= "1001";
			if(modo = "11")then --register mode
				O_BUSCS <= G2B ; --data GR => BIU
				O_GRSEL <= '1'& rm; --set GR
			else                --memory mode
				O_BUSCS <= T22B; --tmpREG2 => BIU
				O_TMPRW <= "00"; --read tmpREG
			end if;
-- REG => stack --------------------------------
--write (SP-2) IR =PUSHms4
		when PUSHrs1 => 
			O_GRSEL <= "1100"; --set SP(GR)
			O_WRIR <= '1'; --write signal to IR
			O_BUSCS <= G2B; --data GR => BIU
			O_TMPRW <= "00";         
	--		EUC_ST <= "1000";
			modov := "00";
			plusv := "001";           -- +1
--write stack
		when PUSHrs2 =>
			O_WR <= '1';
			O_GRSEL <= '1' & I_BDATA(2 downto 0); --set GR
			regv := I_BDATA(2 downto 0);
			O_CSR <= '1'; --CSEG control by EUC
			O_SRSEL <= "10"; --set CSEG to SS
			O_BUSCS <= G2B; --data GR => BIU
	--		EUC_ST <= "1001";
-- Segment REG => stack ------------------------
--write (SP-2) IR =PUSHms4
		when PUSHcs1 => 
			O_GRSEL <= "1100"; --set SP(GR)
			O_WRIR <= '1'; --write signal to IR
			O_BUSCS <= G2B; --data GR => BIU
			O_TMPRW <= "00";         
	--		EUC_ST <= "1000";
			O_RDSR <= '1'; --read CSEG  
			O_CSR <= '1'; --CSEG control by EUC
			O_SRSEL <= I_BDATA(4 downto 3); --seg CSEG
			modov := "00";
			plusv := "001"; -- +1          
--write (CSEG) to temp2 
		when PUSHcs2 => 
			O_RDSR <= '1'; --read CSEG
			O_BUSCS <= B2T2; --data BIU => tmpREG2
			O_TMPRW <= "10"; --write tmpREG2
	--		EUC_ST <= "1001";
		when PUSHcs3 => 
			O_CSR <= '1'; --CSEG control by EUC
			O_SRSEL <= "10"; --set CSEG to SS
			O_WR <= '1';
			O_BUSCS <= T22B; --tmpREG2 => BIU
			O_TMPRW <= "01"; --read tmpREG2
	--		EUC_ST <= "1010";
--POP-------------------------------------------------------------------------
--Register/Memory:::::::::::::::::::::::::::::::::::::::::::::::::::
		when POP1 => 
	--		EUC_ST <= "0011";
			plusv := "010"; -- +2
--SP write to IR
		when POP2 => 
			O_MOD <= I_BDATA(7 downto 6); --output mod		
			modov := I_BDATA(7 downto 6); --ratch mod
			O_RM <= I_BDATA(2 downto 0); --output r/m
			rmv := I_BDATA(2 downto 0);
	--		EUC_ST <= "0100";
			O_GRSEL <= "1100"; --set SP(GR)
			regv := "100"; --set SP(GR)	
			O_WRIR <= '1'; --write signal to IR
			O_BUSCS <= G2B; --data GR => BIU
--read stack
		when POP3 => 
			O_RD <= '1';
			O_CSR <= '1'; --CSEG control by EUC
			O_SRSEL <= "10"; --set CSEG to SS
	--		EUC_ST <= "0101";
--end read stack data,write to Register
		when POPr4 => 
			O_GRSEL <= '1'& rm; --set GR
			O_GRRW <= '1'; --write GR
			O_BUSCS <= B2G; --data BIU => GR
	--		EUC_ST <= "0110";
--end read stack data, write to tmp3
		when POPm4 => 
			O_TMPRW <= "01"; --write tmpREG3
			O_REG3 <= '1'; --use REG3
			O_BUSCS <= B2T1; --data BIU => T1
	---		EUC_ST <= "0110";
--calculate EA
		when POPm5 => 
			O_EA <= '1';	               
	--		EUC_ST <= "0111"; 
--write to memory
		when POPm6 => 
			O_REG3 <= '1'; --use REG3
			O_TMPRW <= "00"; --read tmpREG3
			O_BUSCS <= T12B; --data T1 => BIU
			O_WR <= '1';  
	--		EUC_ST <= "1000";
--SP+2		
		when POP7 => 
			O_2SETTR2 <= '1'; --set 2 to tmpreg2
			O_GRSEL <= "1100"; --set SP(GR)
			regv := "100";
			O_BUSCS <= G2T1; --GR => tmpREG1
			O_TMPRW <= "01"; --write tmpREG1
			O_ALUCS <= KA; --ALU => ADD
	--		EUC_ST <= "1001";
--write(SP+2) to SP
		when POP8 => 
			O_GRRW <= '1'; --write GR
			O_BUSCS <= A2G; --ALU => GR 
			O_GRSEL <= "1100"; --set SP(GR)
	--		EUC_ST <= "1010";
--REGISTER ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
--SP write IR
		when POPreg1 => 
			O_BW <= '1'; --output byte or word		  				
			O_GRSEL <= "1100"; --set SP(GR)
			O_WRIR <= '1'; --write signal to IR
			O_BUSCS <= G2B; --data GR => BIU
			regv := I_BDATA(2 downto 0);
--			EUC_ST <= "0011";
			modov := "00";
			plusv := "001"; -- +1
--read (SP)						
		when POPreg2 => 
			O_RD <= '1';
			O_CSR <= '1'; --CSEG control by EUC
			O_SRSEL <= "10"; --set CSEG to SS
	--		EUC_ST <= "0100";
--end read stack data,write to Register
		when POPreg3 =>
			O_GRSEL <= '1'& reg ; --set GR
			O_GRRW <= '1'; --write GR
			O_BUSCS <= B2G; --data BIU => GR
	--		EUC_ST <= "0101";
--Segment Register ::::::::::::::::::::::::::::::::::::::::::::::::::::
--SP write IR
		when POPsr1 => 
			O_BW <= '1'; --output byte or word
			O_GRSEL <= "1100"; --set SP(GR)
			regv := "100";
			O_WRIR <= '1'; --write signal to IR
			O_BUSCS <= G2B; --data GR => BIU
			modov := I_BDATA(4 downto 3); --latch reg
	--		EUC_ST <= "0011";