ripupeuc2.vhd

X8086的VHDL源码

-----------------------------------
--   FILE NAME : EUC_CU.vhd
--   FUNCTION  : EU Control Unit
--   AUTHOR    : Kazuma Mishima
--   DATE      : 9,10/2001
------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.UPAC.ALL;

entity EUC is
    port( I_CLK        : in std_logic;
          I_RST        : in std_logic;
		  I_BDATA      : in std_logic_vector(7 downto 0); --data from que
	   	  I_QUEEMPTY   : in std_logic; --EMPTY flag
		  I_EARQ       : in std_logic; --END calculate EA => '1'
		  I_ENDRC      : in std_logic; --data out flag from BIU
		  I_ENDWC      : in std_logic; --END write memory
		  O_RD         : out std_logic; --read signal to BIU
	 	  O_WR         : out std_logic; --write signal to BIU
		  O_RDQUE        : out std_logic; --read QUE signal
          O_BUSCS      : out std_logic_vector(4 downto 0); --set data flow
          O_EA         : out std_logic; --calculate EA => '1'
		  O_BW         : out std_logic; --BYTE (0) or WORD (1)
          O_GRSEL      : out std_logic_vector(3 downto 0); --set each GR 
		  O_MOD        : out std_logic_vector(1 downto 0); --mod of OP code 
          O_RM         : out std_logic_vector(2 downto 0); --rm of OP code
          O_TMPRW      : out std_logic_vector(1 downto 0); --read(0) write(1) temp register 1(0) or 2(1) 
          O_ALUCS      : out std_logic_vector(3 downto 0); --control ALU
          O_FRSEL      : out std_logic; --to flag reg '1'=>BUS data '0'=>ALU data
          O_FREN       : out std_logic_vector(17 downto 0);--set flag
          O_GRRW       : out std_logic; --set write(1) or read(0) GR
          O_MULHL      : out std_logic; --MUL => '1'
		  O_CSR        : out std_logic; --'1'=>SSEG from CU |'0'=>SSEG from CSEG
		  O_SRSEL      : out std_logic_vector(1 downto 0); --select Segment Register(BIU)
		  O_WRIP       : out std_logic; --write signal to IP
		  O_WRIR       : out std_logic; --write signal to IR
		  O_WRSR       : out std_logic; --write signal to Segment Registar(BIU)
		  O_1SETTR2    : out std_logic; --temp register2 set 1
		  O_2SETTR2    : out std_logic; --temp register2 set 2
		  O_RDSR       : out std_logic; --read segment REG (write to mem)
		  O_IO         : out std_logic; --access I/O device
		  O_OADR       : out std_logic_vector(15 downto 0); --address when access I/O device 
		  I_DATA       : in std_logic_vector(15 downto 0); --to BIU data
		  O_RDIR       : out std_logic; --read IR
		  O_DIV        : out std_logic; --divid => '1'
		  O_IDIV       : out std_logic; --integer divid => '1',normal divid => '0'
		  O_EAPLUS2    : out std_logic; --to BIU (EA+2)
		  O_MDTF       : out std_logic; --'1' => REGDT <= MEMORY DATA
		  I_ENDDIV     : in std_logic;  --end DIV => '1'
		  I_FREG       : in std_logic_vector(8 downto 0); --Flag 
		  O_REG3       : out std_logic;  --'1' => use tmp3 
		  O_DATA       : out std_logic_vector(15 downto 0); --Out EUC data
		  O_2EU        : out std_logic;  --Set EUC data to EU signal
          O_2BIU       : out std_logic;  --Set EUC data to BIU signal
		  O_2SR        : out std_logic;  --Seg EUC data(address) to Segment Register
		  I_CX         : in std_logic_vector(15 downto 0); --CX data
		  O_USECARRY   : out std_logic;
		  O_ADJUST     : out std_logic_vector(1 downto 0);
		  O_HLT        : out std_logic;  --HALT => '1'
		  O_WRPLUS     : out std_logic;  --plus write signal
          O_PLUSOP     : out std_logic_vector(2 downto 0); --+1,+2,+3,+4,
		  O_PLUSMOD    : out std_logic_vector(1 downto 0); --+1,+2,
          I_NEXTIP     : in std_logic_vector(15 downto 0); --OUT next IP data
		  O_QUERST     : out std_logic; --Reset QUE signal => '1'
		  O_EUCRST     : out std_logic; --OEUC Reset signal
		  O_ADROUT     : out std_logic; --address out memory
		  O_NFE        : out std_logic; --OEUC not fetch signal
		  O_ORPCSR     : out std_logic; --segment override prefix => '1'
		  O_ORPSRSEL   : out std_logic_vector(1 downto 0); --segment register when segment override prefix
		  O_SE         : out std_logic; --sign extension('1'extension,'0'null)
		  O_D16HL      : out std_logic;	-- when 16bit(8bit&8bit)data store to TRU('1'=>high)
		  I_SIGNTR1    : in std_logic;	--for sign check(IMUL)
		  I_BSIGNTR1   : in std_logic;	--for sign check(IMUL)
		  I_REG1       : in std_logic_vector(15 downto 0); --content of the TMP1
		  I_LSBTR2     : in std_logic;	--for MULL (1,0check)
		  O_AAM        : out std_logic;	--set mode(div for AAM)
		  O_MULCS      : out std_logic_vector(1 downto 0); --tmp control 
          O_OP_V       : out std_logic_vector(7 downto 0);
		  O_EUCSTATE_V : out std_logic_vector(8 downto 0)
		  );
	  
end EUC;

architecture RIPUP of EUC is

signal CURRENT_STATE,NEXT_STATE : INSTRUCTION;
signal next_state_s2 : instruction;
signal rdque_s2  : std_logic;
signal bw        : std_logic; --byte or word
signal d         : std_logic; --direction
signal op        : std_logic_vector( 7 downto 0 ); --op code
signal dxx       : std_logic_vector(15 downto 0 ); --ratch address 
signal modo      : std_logic_vector( 1 downto 0 ); --mod
signal rm        : std_logic_vector( 2 downto 0 ); --rm
signal reg       : std_logic_vector( 2 downto 0 ); --reg
signal z         : std_logic; --for REPEAT 
signal plus      : std_logic_vector( 2 downto 0 ); --OPcode PLUS
signal sign      : std_logic; --sign(when IMUL)
signal dest      : std_logic_vector(15 downto 0); --for CALL indirect
signal em_c      : std_logic; --empty cancel signal
signal next_inc  : std_logic_vector( 2 downto 0 );	--plus value(next instruction)  
signal mul_c	 : std_logic_vector( 3 downto 0 );	--shift count variable for mul  
signal alu       : std_logic_vector( 3 downto 0 ); --ALU control 
signal tmp       : std_logic_vector( 7 downto 0 ); --ratch data

signal bwb       : std_logic; --byte or word
signal db        : std_logic; --direction
signal opb       : std_logic_vector( 7 downto 0 ); --op code
signal dxxb      : std_logic_vector(15 downto 0 ); --ratch address 
signal modob     : std_logic_vector( 1 downto 0 ); --mod
signal rmb       : std_logic_vector( 2 downto 0 ); --rm
signal regb      : std_logic_vector( 2 downto 0 ); --reg
signal zb        : std_logic; --for REPEAT 
signal plusb     : std_logic_vector( 2 downto 0 ); --OPcode PLUS
signal signb     : std_logic; --sign(when IMUL)
signal destb     : std_logic_vector(15 downto 0); --for CALL indirect
signal em_cb     : std_logic; --empty cancel signal
signal next_incb : std_logic_vector( 2 downto 0 );	--plus value(next instruction)  
signal mul_cb    : std_logic_vector( 3 downto 0 );	--shift count variable for mul  
signal alub      : std_logic_vector( 3 downto 0 ); --ALU control 
signal tmpb      : std_logic_vector( 7 downto 0 ); --ratch data
begin
--NEXT STATE 
	process(I_CLK,I_RST,NEXT_STATE) 
	begin 
		if(I_CLK'event and I_CLK='0')then
			if(I_RST=RST_ACT)then
				CURRENT_STATE <= S0;
			else				
				CURRENT_STATE <= NEXT_STATE;
			end if;
		end if;          
	end process;            
--SEQUENCE PART

    O_OP_V <= op;

    process(CURRENT_STATE,I_BDATA,bw,reg,modo,rm,tmp,plus,d,op,dxx,mul_c,sign,next_inc,dest,I_DATA,I_LSBTR2,I_BSIGNTR1,alu,z,
			I_SIGNTR1,I_NEXTIP,I_REG1,I_CX,I_FREG)
	variable ex         : std_logic_vector(15 downto 0); --16bit fugou kakuchou
	variable dxxv       : std_logic_vector(15 downto 0); --ratch address 
	variable modov      : std_logic_vector(1 downto 0); --mod
	variable rmv        : std_logic_vector(2 downto 0); --rm
	variable regv       : std_logic_vector(2 downto 0); --reg
	variable zv         : std_logic; --for REPEAT 
	variable plusv      : std_logic_vector(2 downto 0); --OPcode PLUS
	variable signv      : std_logic; --sign(when IMUL)
	variable destv      : std_logic_vector(15 downto 0); --for CALL indirect
	variable next_incv  : std_logic_vector(2 downto 0);	--plus value(next instruction)  
	variable mul_cv     : std_logic_vector(3 downto 0);	--shift count variable for mul  
	variable aluv       : std_logic_vector(3 downto 0); --ALU control 
	variable tmpv       : std_logic_vector(7 downto 0); --ratch data
	begin
        rmv       :=rm;
        dxxv      :=dxx;
        modov     :=modo;
        rmv       :=rm;
        regv      :=reg;
        zv        :=z;
        plusv     :=plus;
        signv     :=sign;
        destv     :=dest;
        next_incv :=next_inc;
        mul_cv    :=mul_c;
        aluv      :=alu;
        tmpv      :=tmp;
		O_EA <= '0';
		O_RD <= '0';
		O_WR <= '0';
		O_BUSCS <= "00000";
		O_GRRW <= '0';
		O_CSR <= '0'; --S_SEG <= CSEG_REG
		O_SRSEL <= "01"; --CS
		O_WRIP <= '0'; --IP 
		O_WRIR <= '0'; --IR
		O_WRSR <= '0'; --not write segment register
		O_TMPRW <= "00"; --tmpreg1 read(initial state) 
		O_2SETTR2 <= '0'; 
		O_RDSR <= '0';
		O_IO <= '0'; --access memory
		O_BW <= bw; --output byte or word
		O_RDIR <= '0'; --not read IR
		O_DIV <= '0'; --not DIVID
		O_IDIV <= '0';
        --OEUC_RorM <= '0'; --register=> '0', memory=> '1'
		O_MULHL <= '0'; --not MUL
		O_MDTF <= '0'; --REGDT <= EU
		O_EAPLUS2 <= '0'; --not EA+2
		O_FRSEL <= '0'; --ALU data
        O_FREN <= "010101010101010101"; --not write flag register 
        O_REG3 <= '0'; --not use REG3
		O_DATA <= "0000000000000000"; --Out EUC data
	    O_2EU <= '0'; --not Out O_DATA
		O_2BIU <= '0'; --EU data to BIU
		O_2SR <= '0'; --not Out O_DATA(address) to Segment registar				
		O_1SETTR2 <= '0'; --not write tmp2 = '1'
		O_SE <= '0';
		O_USECARRY <= '0';
 	    O_ADJUST <= "00";
		O_HLT <= '0'; --not HALT
--		EUC_ST <= "0000";                    
        O_QUERST <= '0'; --not reset que
		O_EUCRST <= '0'; --not reset
		O_ADROUT <= '0'; --not address out to memory
		O_NFE <= '0'; --possible fetch 
		O_ORPCSR <= '0'; --not segment override prefix					 
		O_GRSEL <= bw & reg;
	    O_MOD <= modo; --mod of OP code 
        O_RM <= rm; --rm of OP code (BX+SI)
		O_ALUCS <= KA ;             --control ALU
        O_RDSR <= '0';               --read segment REG (write to mem)
	    O_OADR <= (others => '0');   --address when access I/O device 
		O_WRPLUS <= '0';             --plus write signal
        O_PLUSOP <= "000"; --+1,+2,+3,+4,
		O_PLUSMOD <= "00"; --+1,+2,
        O_ORPSRSEL <= "00"; --segment register when segment override prefix
		O_D16HL <= '0';
		O_AAM <= '0'; --set mode(div for AAM)
		O_MULCS <= "00";
		case CURRENT_STATE is
--initial state		    
		when S0 => 
			O_BW <= '1'; --output byte or word
--			EUC_ST <= "0000";        
			O_GRSEL <= "0000"; --set each GR(AX,AL) 
			O_MOD <= "00"; --mod of OP code 
			O_RM <= "000"; --rm of OP code (BX+SI)
			--NEXT IP
			if(plus="001" or plus="010" or plus="011" or plus="100")then --when plus
				O_WRPLUS <= '1';
				O_PLUSOP <= plus;
				if   (modo="01")then
					O_PLUSMOD <= "01";
				elsif(modo="10")then
					O_PLUSMOD <= "10";
				else
					O_PLUSMOD <= "00";
				end if;
			else
				O_WRPLUS <= '0';
				O_PLUSOP <= "000";
				O_PLUSMOD <= "00";
			end if;
--wait fetch 
		when S00 => 
--			EUC_ST <= "0010";
			O_WRPLUS <= '0';
			plusv := "000";
			modov := "00";
			rmv := "000";
			O_BW <= '1'; --output byte or word
			O_MOD <= "00"; --mod of OP code 
            O_RM <= "000"; --rm of OP code (BX+SI)
--read OP code from QUE
		when S1 => 
			O_WRPLUS <= '0';			          
			O_MOD <= "00"; --mod of OP code 
            O_RM <= "000"; --rm of OP code (BX+SI)
--			EUC_ST <= "0001";        
			plusv := "000";
			modov := "00";
			rmv := "000";
			--regv := "000";
			--tmpv :="00000000";
			O_BW <= '1'; --output byte or word						
--wait OP code
		when S2 => 			 			
			O_MOD <= "00"; --mod of OP code 
			O_RM <= "000"; --rm of OP code (BX+SI)
			--regv := "000";
			--tmpv :="00000000";
			modov := "00";
			rmv := "000";
--			EUC_ST <= "0010";
--MOV---------------------------------------------------------------------------------------							 
--input OP code
		when MOV1=> 
--			EUC_ST <= "0011";
			plusv := "010"; -- +2
		when MOV2 => 
			O_MOD <= I_BDATA(7 downto 6); --output mod		
	        modov := I_BDATA(7 downto 6); --ratch mod
			O_RM <= I_BDATA(2 downto 0); --output r/m
			rmv := I_BDATA(2 downto 0);
--			EUC_ST <= "0100";
			O_ALUCS <= KA; --ALU => ADD
			if(I_BDATA(7 downto 6)= "11")then --register => register			                
				O_BUSCS <= G2T1; --GR => tmpREG1
				O_TMPRW <= "01"; --write tmpREG1
				if(d='1')then --rm => reg
					O_GRSEL <= bw & I_BDATA(2 downto 0); --set GR
					regv := I_BDATA(2 downto 0);
				else          --reg => rm
					O_GRSEL <= bw & I_BDATA(5 downto 3); --set GR
					regv := I_BDATA(5 downto 3);
				end if;									
			else --memory=>register or register=>memory
				O_EA <= '1'; --calculate EA 			                
				O_GRSEL <= bw & I_BDATA(5 downto 3); --set GR
				regv := I_BDATA(5 downto 3);
			end if;
--wait calculate EA
		when MOV3 => 
--			EUC_ST <= "0101";						  				  							
			O_EA <= '1';
--MOV reg=>reg 
		when MOVrr => 
			O_GRRW <= '1'; --write GR
            O_BUSCS <= T12G; --tmpREG1 => GR
--			EUC_ST <= "0110";
			if(d='1')then --rm => reg
				O_GRSEL <= op(0) & I_BDATA(5 downto 3); --set GR
				regv := I_BDATA(5 downto 3);
			else          --reg => rm
				O_GRSEL <= op(0) & I_BDATA(2 downto 0); --set GR
				regv := I_BDATA(2 downto 0);
			end if;									
--MOV mem=>reg 1						  							        
		when MOVmr => 
			O_RD <= '1';
--			EUC_ST <= "0111";
--MOV mem=>reg 2
		when MOVmr2 => 
			O_GRRW <= '1'; --write GR
			O_BUSCS <= B2G;  --data BIU => GR
--			EUC_ST <= "1000";
--MOV reg=>mem
		when MOVrm => 
			O_BUSCS <= G2B; --out data GR => BIU
			O_WR <= '1';
--			EUC_ST <= "1001";
-- MOVi immediate data write mem/reg ::::::::::::::::::::::::::::::::::::::::::
		when MOVi1=> 
--			EUC_ST <= "0011";
			if(bw='0')then
				plusv := "011"; -- +3
			else
				plusv := "100"; -- +4
			end if;
		when MOVi2 => 
			O_MOD <= I_BDATA(7 downto 6); --output mod		
	        modov := I_BDATA(7 downto 6); --ratch mod
			O_RM <= I_BDATA(2 downto 0); --output r/m
			rmv := I_BDATA(2 downto 0); --ratch rm
--			EUC_ST <= "0100";
			O_ALUCS <= KA; --ALU => ADD
			regv := I_BDATA(2 downto 0);
			if(I_BDATA(7 downto 6)= "11")then -- => register			                
				O_GRSEL <= bw & I_BDATA(2 downto 0); --set GR
			else                                   -- =>memory
				O_EA <= '1'; --calculate EA 			                
			end if;
--wait calculate EA
		when MOVi3 => 
--			EUC_ST <= "0101";
			O_EA <= '1';
-- =>register
--wait que data
		when MOVir3 => null;
--			EUC_ST <= "0110";
--read 1 byte data
		when MOVir4 => 
--			EUC_ST <= "0111";
			if(bw = '1')then
				tmpv := I_BDATA(7 downto 0);
			else
				O_DATA <= "00000000" & I_BDATA(7 downto 0); --out bus immediate data
				O_2EU <= '1'; --out EUC data signal
				O_GRRW <= '1';  --write GR
				O_BUSCS <= B2G;   --data BIU => GR
			end if;
--wait que data
		when MOVir5 => null;
--			EUC_ST <= "1000";
--read end word data,write GR
		when MOVir6 =>  
			O_DATA <= I_BDATA(7 downto 0) & tmp; --out bus immediate data
			O_2EU <= '1'; --EUC data to EU
			O_GRRW <= '1';  --write GR
            O_BUSCS <= B2G;   --data BIU => GR
--			EUC_ST <= "1001";
-- =>memory	
--end calculate EA,wait que data
		when MOVim3 => 
--			EUC_ST <= "1010";
			O_EA <= '0';
--wait que data
		when MOVim4 => null;
--			EUC_ST <= "1011";
--read 1 byte data
		when MOVim5 =>