ir.vhd

来自「X8086的VHDL源码」· VHDL 代码 · 共 44 行

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--   FILE NAME : IR_IPIR.vhd
--   FUNCTION  : Internal Register(ratch EA)
--   AUTHOR    : Kazuma Mishima
--   DATE      : 7/2001
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.UPAC.all;

entity IR is
    port( I_CLK    :  in std_logic;
          I_RST    :  in std_logic;
		  I_WRIR   :  in std_logic; --write signal from EUC  
		  I_EARQ   :  in std_logic;--EA out => '1' 
		  I_DATA   :  in std_logic_vector(15 downto 0); 
          O_IRDATA : out std_logic_vector(15 downto 0)
		  ); 
end IR;

architecture RTL of IR is

signal ir : std_logic_vector(15 downto 0); --Internal Register

begin

	O_IRDATA <= ir;
   
	INTERNAL_REGISTER : 
	process(I_CLK,I_RST,I_EARQ,I_WRIR,I_DATA)
	begin
		if (I_RST = RST_ACT) then
			ir <= "0000000000000000";
		elsif (I_CLK'event and I_CLK='0') then
		--WRITE to IR
			if (I_EARQ = '1' or I_WRIR = '1')then --end calculate EA or active write signal
				ir <= I_DATA;
			end if;
		end if;
	end process;

end RTL;