eu.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library synplify;
use synplify.attributes.all;
 
entity EU is
	port( I_CLK       : in std_logic;
		  I_RST       : in std_logic;
          I_S77       : in std_logic;
          I_ALUCS     : in std_logic_vector( 3 downto 0 );
          I_BW        : in std_logic;
          I_BIUDATA   : in std_logic_vector(15 downto 0 );
          I_BUSCS     : in std_logic_vector( 4 downto 0 );
          I_D16HL     : in std_logic;
          I_FRSEL     : in std_logic;
          I_DIVF      : in std_logic;
          I_EA        : in std_logic;
          I_FREN      : in std_logic_vector(17 downto 0 );
          I_GRRW      : in std_logic;
          I_GRSEL     : in std_logic_vector( 3 downto 0 );
          I_MULHL     : in std_logic;
          I_QUOF      : in std_logic;
          I_TMPRW     : in std_logic_vector( 1 downto 0 );
          I_TMPCS     : in std_logic_vector( 4 downto 0 );
          I_1SETTR2   : in std_logic;
          I_ADJUST    : in std_logic_vector( 1 downto 0 );
          I_MULCS     : in std_logic_vector( 1 downto 0 );
          I_REG3      : in std_logic;
          I_SE        : in std_logic;
          I_2SETTR2   : in std_logic;
          I_USECARRY  : in std_logic;
          O_QUOF      : out std_logic;
          O_EUDATA    : out std_logic_vector(15 downto 0 );
          O_FREG      : out std_logic_vector( 8 downto 0 );
          O_SIGNDIV   : out std_logic;
          O_BSIGNDIV  : out std_logic;
          O_SIGNTR1   : out std_logic;
          O_SIGNPLS   : out std_logic;
          O_BSIGNTR1  : out std_logic;
          O_SIGNTR2   : out std_logic;
          O_LSBTR2    : out std_logic;
	      O_ALUDATA_V : out std_logic_vector(15 downto 0 );
          O_REG1      : out std_logic_vector(15 downto 0 );
          O_REG2      : out std_logic_vector(15 downto 0 );
          O_AX_V      : out std_logic_vector(15 downto 0 );
          O_BP_V      : out std_logic_vector(15 downto 0 );
          O_BX_V      : out std_logic_vector(15 downto 0 );
          O_CX_V      : out std_logic_vector(15 downto 0 );
          O_DI_V      : out std_logic_vector(15 downto 0 );
          O_DX_V      : out std_logic_vector(15 downto 0 );
          O_SI_V      : out std_logic_vector(15 downto 0 );
          O_SP_V      : out std_logic_vector(15 downto 0 )
          );
end EU;
 
architecture RTL of EU is
 
signal ALU_ALUDATA    : std_logic_vector(15 downto 0 );
signal ALU_FREGST     : std_logic_vector( 5 downto 0 );
signal FR_CFR         : std_logic;
signal FR_AFR         : std_logic;
signal FR_FREG        : std_logic_vector( 8 downto 0 );
signal EUINBUS_GREG   : std_logic_vector(15 downto 0 );
signal GRU_GREG       : std_logic_vector(15 downto 0 );
signal TRUIO_TMPCS    : std_logic_vector( 4 downto 0 );
signal TRU_BO         : std_logic;
signal TRU_TREG1      : std_logic_vector(15 downto 0 );
signal TRU_TREG2      : std_logic_vector(15 downto 0 );
signal TRU_TR1PLS2ALU : std_logic_vector(15 downto 0 );
signal TRU_TR2DIV2ALU : std_logic_vector(15 downto 0 );
signal EUINBUS_FREG   : std_logic_vector( 8 downto 0 );
signal EUINBUS_TREG1  : std_logic_vector(15 downto 0 );
signal EUINBUS_TREG2  : std_logic_vector(15 downto 0 );

component GRU
	port( I_CLK   :  in std_logic;
		  I_RST   :  in std_logic;
          I_S77   :  in std_logic;
          I_GRRW  :  in std_logic;
          I_GRSEL :  in std_logic_vector( 3 downto 0 );
     	  I_GREG  :  in std_logic_vector(15 downto 0 );
		  O_GREG  : out std_logic_vector(15 downto 0 );
		  O_AX_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_BX_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_CX_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_DX_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_SP_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_BP_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_DI_V  : out std_logic_vector(15 downto 0 ); --for test
		  O_SI_V  : out std_logic_vector(15 downto 0 ) --for test
		  );
end component;

component INBUS
	port( I_BUSCS	 :  in std_logic_vector ( 4 downto 0);
		  I_TREG1    :  in std_logic_vector (15 downto 0);
      	  I_TREG2    :  in std_logic_vector (15 downto 0);
          I_GREG 	 :  in std_logic_vector (15 downto 0);
          I_ALUDATA  :  in std_logic_vector (15 downto 0);
          I_BIUDATA  :  in std_logic_vector (15 downto 0);
          I_FREG	 :  in std_logic_vector ( 8 downto 0);
          O_TREG1    : out std_logic_vector (15 downto 0);
	      O_TREG2    : out std_logic_vector (15 downto 0);
	      O_GREG     : out std_logic_vector (15 downto 0);
          O_EUDATA   : out std_logic_vector (15 downto 0);
          O_FREG     : out std_logic_vector ( 8 downto 0)
		  );
end component;

component FR
	port( I_CLK   :  in std_logic;
          I_RST   :  in std_logic;
          I_STFR  :  in std_logic_vector( 5 downto 0 );
          I_FRSEL :  in std_logic;
          I_FREN  :  in std_logic_vector(17 downto 0 );
          I_FREG  :  in std_logic_vector( 8 downto 0 );
		  O_CFR   : out std_logic;
		  O_AFR   : out std_logic;
          O_FREG  : out std_logic_vector( 8 downto 0 )
          ); 
end component;

component TRU
 	port( I_CLK      :  in std_logic;
		  I_RST      :  in std_logic;
		  I_TREG1    :  in std_logic_vector(15 downto 0 );
		  I_TREG2    :  in std_logic_vector(15 downto 0 );
          I_TMPRW    :  in std_logic_vector( 1 downto 0 );
          I_D16HL    :  in std_logic;
          I_BW       :  in std_logic;
          I_DIVF     :  in std_logic;
		  I_QUOF     :  in std_logic;
		  I_MULCS    :  in std_logic_vector( 1 downto 0 );
		  I_2SETTR2	 :  in std_logic; --for sp+2
		  I_1SETTR2  :  in std_logic; --for INC('1':set 1 to tmp2)
		  I_REG3	 :  in std_logic; --for reg3
		  I_TMPCS	 :  in std_logic_vector( 4 downto 0 );
		  I_SE       :  in std_logic; --for sign extension("1"extension,"0"null)
		  O_TREG1    : out std_logic_vector(15 downto 0 );
		  O_TREG2    : out std_logic_vector(15 downto 0 );
		  O_SIGNPLS  : out std_logic; --for idiv(sign check)
		  O_SIGNDIV  : out std_logic; --for idiv(sign check)
		  O_BSIGNDIV : out std_logic; --for idiv(sign check)
		  O_SIGNTR1  : out std_logic; --for idiv(sign check)
		  O_BSIGNTR1 : out std_logic; --for idiv(sign check)
		  O_SIGNTR2  : out std_logic; --for idiv(sign check)
		  O_LSBTR2   : out std_logic; --for MUL(reg2(0):1,0check)
		  O_BORROW   : out std_logic;
		  O_REG1 	 : out std_logic_vector(15 downto 0 );	--for test
		  O_REG2 	 : out std_logic_vector(15 downto 0 );	--for test
          O_TR1PLS   : out std_logic_vector(15 downto 0 );
		  O_TR2DIV   : out std_logic_vector(15 downto 0 )
		  );
end component;

component ALU
	port( I_TR1PLS    :  in std_logic_vector(15 downto 0);
          I_TR2DIV    :  in std_logic_vector(15 downto 0);
          I_ALUCS     :  in std_logic_vector( 3 downto 0);
          I_BW    	  :  in std_logic;
		  I_EA		  :  in std_logic; --for b_w
          I_MULHL 	  :  in std_logic;
		  I_USECARRY  :  in std_logic; --for use carry(<='1')
		  I_ADJUST	  :  in std_logic_vector( 1 downto 0); --for ADJUST(AAA,DAA,AAS,DAS)
		  I_BORROW 	  :  in std_logic; --for div
          I_CFR	      :  in std_logic;
		  I_AFR       :  in std_logic;
		  I_DIVF	  :  in std_logic; --for div
		  O_QUOF      : out std_logic; --for div(quotient set)
          O_STFR	  : out std_logic_vector( 5 downto 0); --status flag
		  O_ALUDATA_V : out std_logic_vector(15 downto 0); --for test
          O_ALUDATA   : out std_logic_vector(15 downto 0)
		  );
end component;
component TRUIO
    port( I_REG3  :  in std_logic;
          I_TMPCS :  in std_logic_vector( 4 downto 0 );
          I_DIVF  :  in std_logic;
          I_TMPRW :  in std_logic_vector( 1 downto 0 );
	 	  I_MULCS :  in std_logic_vector( 1 downto 0 );	
          O_TMPCS : out std_logic_vector( 4 downto 0 )
		  );
end component;
 
begin
 
	GRU_EU : GRU
	port map( 
		I_CLK => I_CLK,
		I_RST => I_RST,
        I_S77 => I_S77,
        I_GRRW => I_GRRW, 
        I_GRSEL => I_GRSEL,
     	I_GREG => EUINBUS_GREG,
		O_GREG => GRU_GREG,
		O_AX_V => O_AX_V,
		O_BX_V => O_BX_V,
		O_CX_V => O_CX_V,
		O_DX_V => O_DX_V,
		O_SP_V => O_SP_V,
		O_BP_V => O_BP_V,
		O_DI_V => O_DI_V,
		O_SI_V => O_SI_V
		);
 
	INBUS_EU : INBUS
	port map( 
        I_BUSCS => I_BUSCS,
		I_TREG1 => TRU_TREG1,
      	I_TREG2 => TRU_TREG2,
        I_FREG => FR_FREG,
        I_GREG => GRU_GREG,
        I_ALUDATA => ALU_ALUDATA,
        I_BIUDATA => I_BIUDATA,
        O_TREG1 => EUINBUS_TREG1,
	    O_TREG2 => EUINBUS_TREG2,
	    O_GREG => EUINBUS_GREG,
        O_EUDATA => O_EUDATA,
        O_FREG => EUINBUS_FREG
		);

	FR_EU : FR
	port map( 
		I_CLK => I_CLK,
        I_RST => I_RST,
        I_STFR => ALU_FREGST,
        I_FRSEL => I_FRSEL,
        I_FREN => I_FREN,
        I_FREG => EUINBUS_FREG,
		O_CFR => FR_CFR,
		O_AFR => FR_AFR,
        O_FREG => FR_FREG
        ); 

	TRU_EU : TRU
	port map( 
       	I_CLK => I_CLK,
		I_RST => I_RST,
		I_TREG1 => EUINBUS_TREG1,
		I_TREG2 => EUINBUS_TREG2,
        I_TMPRW => I_TMPRW,
        I_D16HL => I_D16HL,
        I_BW => I_BW,
        I_DIVF => I_DIVF,
		I_QUOF => I_QUOF,
		I_MULCS => I_MULCS,
		I_2SETTR2 => I_2SETTR2,
		I_REG3 => I_REG3,
		I_TMPCS => TRUIO_TMPCS,
		I_SE => I_SE,
		I_1SETTR2 => I_1SETTR2,
		O_TREG1 => TRU_TREG1,
		O_TREG2 => TRU_TREG2,
		O_SIGNPLS => O_SIGNPLS,
		O_SIGNDIV => O_SIGNDIV,  
		O_BSIGNDIV => O_BSIGNDIV,
		O_SIGNTR1 => O_SIGNTR1,
		O_BSIGNTR1 => O_BSIGNTR1,
		O_SIGNTR2 => O_SIGNTR2,
		O_LSBTR2 => O_LSBTR2,
		O_BORROW => TRU_BO,
		O_REG1 => O_REG1,
		O_REG2 => O_REG2,
        O_TR1PLS => TRU_TR1PLS2ALU,
		O_TR2DIV => TRU_TR2DIV2ALU
		);

	ALU_EU : ALU
	port map( 
		I_TR1PLS => TRU_TR1PLS2ALU,
        I_TR2DIV => TRU_TR2DIV2ALU,
        I_ALUCS => I_ALUCS,
        I_BW => I_BW,
		I_EA => I_EA,
        I_MULHL => I_MULHL,
		I_USECARRY => I_USECARRY,
		I_ADJUST => I_ADJUST,
		I_BORROW => TRU_BO,
        I_CFR => FR_CFR,
		I_AFR => FR_AFR,
		I_DIVF => I_DIVF,
		O_QUOF => O_QUOF,
        O_STFR => ALU_FREGST,
		O_ALUDATA_V => O_ALUDATA_V,
        O_ALUDATA => ALU_ALUDATA
		);
 
	TRUIO_EU : TRUIO
    port map( 
		I_REG3 => I_REG3,
        I_TMPCS => I_TMPCS,
        I_DIVF => I_DIVF,
        I_TMPRW => I_TMPRW,
	 	I_MULCS => I_MULCS,
        O_TMPCS => TRUIO_TMPCS
		);

	O_FREG <= FR_FREG;

end RTL;