mp8086.saf

X8086的VHDL源码

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
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# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Signal Activity File Name: "C:/work/MP8086/MP8086.saf"
# Created On: "01/10/2007 15:59:24"
# Created By: "Version 6.0 Build 178 04/27/2006 SJ Full Version"
# This file was created by the Quartus(R) II Simulator with glitch filtering enabled.

FORMAT_VERSION 1;

DEFINE_FLAG TOGGLE_RATE_FROM_SIMULATION 0x1;
DEFINE_FLAG STATIC_PROBABILITY_FROM_SIMULATION 0x2;
DEFINE_FLAG TOGGLE_RATE_FROM_USER 0x4;
DEFINE_FLAG STATIC_PROBABILITY_FROM_USER 0x8;
DEFINE_FLAG TOGGLE_RATE_FROM_USER_DEFAULT 0x10;
DEFINE_FLAG STATIC_PROBABILITY_FROM_USER_DEFAULT 0x20;
DEFINE_FLAG TOGGLE_RATE_FROM_VECTORLESS_ESTIMATION 0x40;
DEFINE_FLAG STATIC_PROBABILITY_FROM_VECTORLESS_ESTIMATION 0x80;
DEFINE_FLAG TOGGLE_RATE_ASSUMED_ZERO 0x100;
DEFINE_FLAG TOGGLE_RATE_CLIPPED_TO_MAX 0x200;

BEGIN_OUTPUT_SIGNAL_INFO;

# Output Signal Information Line Format Description:

# <one or more spaces><partial output signal name><spaces>[<flags mask><spaces><toggle rate><spaces><static probability>]<;>

 CONV7SEG:CONV7SEG_MP8086;
  G_24 0x3 0 0;
  G_27 0x3 0 0;
  G_36 0x3 0 1;
  G_66 0x3 0 0;
  o_7segdata1_5 0x3 0 0;
  o_7segdata1_19 0x3 0 1;
  o_7segdata1_24 0x3 0 1;
  o_7segdata1_28 0x3 0 1;
  o_7segdata1_36 0x3 0 0;
  o_7segdata1_38 0x3 0 0;
  o_7segdata1_41 0x3 0 0;
  o_7segdata2_5 0x3 0 0;
  o_7segdata2_19 0x3 0 1;
  o_7segdata2_24 0x3 0 1;
  o_7segdata2_28 0x3 0 1;
  o_7segdata2_36 0x3 0 1;
  o_7segdata2_38 0x3 0 0;
  o_7segdata2_41 0x3 0 1;
  o_7segdata3_5 0x3 0 0;
  o_7segdata3_19 0x3 0 1;
  o_7segdata3_24 0x3 0 1;
  o_7segdata3_28 0x3 0 1;
  o_7segdata3_36 0x3 0 0;
  o_7segdata3_38 0x3 0 0;
  o_7segdata3_41 0x3 0 0;
  o_7segdata4_5 0x3 0 1;
  o_7segdata4_19 0x3 0 0;
  o_7segdata4_24 0x3 0 1;
  o_7segdata4_28 0x3 0 1;
  o_7segdata4_36 0x3 0 1;
  o_7segdata4_38 0x3 0 1;
  o_7segdata4_41 0x3 0 1;
  o_7segdata5_5 0x3 0 1;
  o_7segdata5_19 0x3 0 1;
  o_7segdata5_24 0x3 0 1;
  o_7segdata5_28 0x3 0 1;
  o_7segdata5_36 0x3 0 0;
  o_7segdata5_38 0x3 0 0;
  o_7segdata5_41 0x3 0 0;
  o_7segdata6_5 0x3 0 1;
  o_7segdata6_19 0x3 0 1;
  o_7segdata6_24 0x3 0 1;
  o_7segdata6_28 0x3 0 1;
  o_7segdata6_36 0x3 0 0;
  o_7segdata6_38 0x3 0 0;
  o_7segdata6_41 0x3 0 0;
  o_7segdata7_2 0x3 0 1;
  o_7segdata7_5 0x3 0 1;
  o_7segdata7_19 0x3 0 1;
  o_7segdata7_24 0x3 0 1;
  o_7segdata7_28 0x3 0 1;
  o_7segdata7_36 0x3 0 0;
  o_7segdata7_38 0x3 0 0;
  o_7segdata8_24 0x3 0 0;
  o_7segdata8_28 0x3 0 1;
  o_7segdata8_36 0x3 0 0;
  o_7segdata8_38 0x3 0 0;
  o_7segdata8_40 0x3 0 1;
  o_7segdata8_41 0x3 0 1;
 G_3288 0x3 0 0;
 G_4764_5192 0x3 0 1;
 G_4764_5194 0x3 0 1;
 G_4764_5197 0x3 0 1;
 G_4764_5201 0x3 333.333 0.966666;
 G_7975 0x3 0 1;
 G_7979 0x3 0 1;
 G_7987 0x3 0 1;
 G_7991 0x3 0 1;
 G_7994 0x3 0 1;
 G_7996 0x3 0 1;
 G_8006_2 0x3 0 1;
 G_8007_1 0x3 0 0;
 G_8009 0x3 0 0;
 G_8017_2 0x3 0 1;
 G_8019 0x3 0 0;
 G_8020 0x3 0 0;
 G_8021 0x3 0 1;
 G_8027 0x3 0 0;
 G_8030_1 0x3 0 1;
 G_8030_2 0x3 0 1;
 G_8030_3 0x3 0 1;
 G_8031 0x3 0 1;
 G_8031_1 0x3 0 1;
 G_8033 0x3 0 1;
 G_8034 0x3 0 1;
 G_8036 0x3 0 1;
 G_8037 0x3 0 1;
 G_8040 0x3 0 1;
 G_8041 0x3 0 1;
 G_8042 0x3 0 1;
 G_8044 0x3 0 1;
 G_8045 0x3 0 1;
 G_8046 0x3 0 1;
 G_8047 0x3 0 1;
 G_8048_1 0x3 0 0;
 G_8051_1 0x3 0 1;
 G_8055_1 0x3 0 0;
 G_8055_2 0x3 0 0;
 G_8055_3 0x3 0 0;
 G_8059 0x3 0 0;
 G_8064 0x3 0 0;
 G_8071_1 0x3 266.667 0.373333;
 G_8071_3 0x3 0 0;
 G_8071_5 0x3 333.333 0.04;
 G_8071_18 0x3 466.667 0.393333;
 G_8071_19 0x3 0 0;
 G_8071_21 0x3 0 0;
 G_8071_22 0x3 0 0;
 G_8071_23 0x3 0 0;
 G_8071_24 0x3 0 0;
 G_8071_25 0x3 0 0;
 G_8071_26 0x3 0 0;
 G_8071_28 0x3 333.333 0.04;
 G_8071_32 0x3 0 0;
 G_8071_33 0x3 600 0.433333;
 G_8094 0x3 0 0;
 G_8096 0x3 0 0;
 G_8101 0x3 0 0;
 G_8103 0x3 0 0;
 G_8108 0x3 0 0;
 G_8110 0x3 0 0;
 G_8118 0x3 0 0;
 G_8121 0x3 0 0;
 G_8122 0x3 0 0;
 G_8127 0x3 0 0;
 G_8128 0x3 0 0;
 G_8147 0x3 0 0;
 G_8152 0x3 0 0;
 G_8155 0x3 0 0;
 G_8159 0x3 0 0;
 G_8161 0x3 0 0;
 G_8162 0x3 0 0;
 G_8163 0x3 0 0;
 G_8164 0x3 0 0;
 G_8166 0x3 0 0;
 G_8168 0x3 0 0;
 G_8169 0x3 0 0;
 G_8171 0x3 266.667 0.373333;
 G_8172 0x3 0 0;
 G_8177 0x3 0 0;
 G_8186 0x3 0 0;
 G_8189 0x3 0 0;
 G_8192 0x3 0 0;
 G_8193 0x3 0 0;
 G_8195 0x3 0 0;
 G_8196 0x3 0 0;
 G_8202 0x3 0 0;
 G_8204 0x3 0 0;
 G_8206 0x3 0 0;
 G_8209 0x3 0 0;
 G_8213 0x3 0 0;
 G_8214 0x3 0 0;
 G_8217 0x3 0 0;
 G_8219 0x3 0 0;
 G_8222 0x3 0 0;
 G_8224 0x3 200 0.02;
 G_8225 0x3 0 0;
 G_8227 0x3 0 0;
 G_8230 0x3 0 0;
 G_8231 0x3 0 0;
 G_8234 0x3 266.667 0.373333;
 G_8235 0x3 0 0;
 G_8242 0x3 0 0;
 G_8268 0x3 0 0;
 G_8274 0x3 333.333 0.0333333;
 G_8290 0x3 0 0;
 G_8292 0x3 0 0;
 G_8293 0x3 0 0;
 G_8294 0x3 0 0;
 G_8303 0x3 0 0;
 HMEM:HMEM_MP8086;
  LPM_RAM_DPZ0:lpm_ram_dp_component;
   lpm_ram_dp:U1;
    altdpram:sram;
     altsyncram:ram_block;
      altsyncram_jas1:auto_generated;
       q_b[0] 0x3 133.333 0.213333;
       q_b[1] 0x3 0 0;
       q_b[2] 0x3 0 0;
       q_b[3] 0x3 0 0;
       q_b[4] 0x3 0 0;
       q_b[5] 0x3 0 0;
       q_b[6] 0x3 0 0;
       q_b[7] 0x3 0 0;
 I_4000 0x3 0 0;
 I_4000_6249 0x3 0 0;
 I_4011_7195 0x3 0 0;
 I_4021_5504 0x3 333.333 0.966667;
 I_4021_5507 0x3 0 0;
 I_4049_5486 0x3 0 1;
 I_4049_5488 0x3 0 1;
 I_4049_5489 0x3 0 1;
 I_4051 0x3 66.6667 0.986667;
 I_4054 0x3 0 0;
 I_4055 0x3 0 0;
 I_4060_4789 0x3 0 0;
 I_4061 0x3 0 0;
 I_4061_5103 0x3 0 0;
 I_4146 0x3 0 1;
 I_4161_6509 0x3 0 1;
 I_4345 0x3 0 0;
 I_4378_5059 0x3 533.333 0.106667;
 I_4383 0x3 266.667 0.28;
 I_4391 0x3 66.6667 0.28;
 I_4399 0x3 133.333 0.133333;
 I_4407 0x3 0 0;
 I_4415 0x3 0 0;
 I_4423 0x3 200 0.2;
 I_4431 0x3 133.333 0.133333;
 I_4439 0x3 266.667 0.28;
 I_CLK 0x3 9966.67 0.5;
 I_RDY 0x3 0 1;
 I_RST 0x3 66.6667 0.984058;
 I_S77 0x3 0 1;
 LMEM:LMEM_MP8086;
  lpm_ram_dpZ0:lpm_ram_dp_component;
   lpm_ram_dp:U1;
    altdpram:sram;
     altsyncram:ram_block;
      altsyncram_6cs1:auto_generated;
       q_b[0] 0x3 266.667 0.28;
       q_b[1] 0x3 66.6667 0.28;
       q_b[2] 0x3 133.333 0.133333;
       q_b[3] 0x3 0 0;
       q_b[4] 0x3 0 0;
       q_b[5] 0x3 200 0.2;
       q_b[6] 0x3 133.333 0.133333;
       q_b[7] 0x3 266.667 0.28;
 MCU:MCU_MP8086;
  O_ADR_0 0x3 233.333 0.286667;
  O_ADR_1 0x3 166.667 0.686667;
  O_ADR_2 0x3 233.333 0.24;
  O_ADR_3 0x3 366.667 0.506667;
  O_ADR_4 0x3 366.667 0.506667;
  O_ADR_5 0x3 366.667 0.506667;
  O_ADR_6 0x3 366.667 0.506667;
  O_ADR_7 0x3 100 0.906667;
  O_WRH_0_and2 0x3 200 0.04;
  O_WRL_0_and2 0x3 200 0.04;
  adr[0] 0x3 0 0;
 N_4090_i 0x3 0 0;
 N_6425_i 0x3 666.667 0.126667;
 O_7SEGDATA1[0] 0x3 0 0;
 O_7SEGDATA1[1] 0x3 0 1;
 O_7SEGDATA1[2] 0x3 0 1;
 O_7SEGDATA1[3] 0x3 0 1;
 O_7SEGDATA1[4] 0x3 0 1;
 O_7SEGDATA1[5] 0x3 0 1;
 O_7SEGDATA1[6] 0x3 0 1;
 O_7SEGDATA1[7] 0x3 0 1;
 O_7SEGDATA2[0] 0x3 0 0;
 O_7SEGDATA2[1] 0x3 0 1;
 O_7SEGDATA2[2] 0x3 0 0;
 O_7SEGDATA2[3] 0x3 0 0;
 O_7SEGDATA2[4] 0x3 0 1;
 O_7SEGDATA2[5] 0x3 0 1;
 O_7SEGDATA2[6] 0x3 0 1;
 O_7SEGDATA2[7] 0x3 0 1;
 O_7SEGDATA3[0] 0x3 0 0;
 O_7SEGDATA3[1] 0x3 0 1;
 O_7SEGDATA3[2] 0x3 0 1;
 O_7SEGDATA3[3] 0x3 0 1;
 O_7SEGDATA3[4] 0x3 0 1;
 O_7SEGDATA3[5] 0x3 0 1;
 O_7SEGDATA3[6] 0x3 0 1;
 O_7SEGDATA3[7] 0x3 0 1;
 O_7SEGDATA4[0] 0x3 0 0;
 O_7SEGDATA4[1] 0x3 0 0;
 O_7SEGDATA4[2] 0x3 0 0;
 O_7SEGDATA4[3] 0x3 0 0;
 O_7SEGDATA4[4] 0x3 0 0;
 O_7SEGDATA4[5] 0x3 0 1;
 O_7SEGDATA4[6] 0x3 0 1;
 O_7SEGDATA4[7] 0x3 0 0;
 O_7SEGDATA5[0] 0x3 0 0;
 O_7SEGDATA5[1] 0x3 0 0;
 O_7SEGDATA5[2] 0x3 0 1;
 O_7SEGDATA5[3] 0x3 0 1;
 O_7SEGDATA5[4] 0x3 0 1;
 O_7SEGDATA5[5] 0x3 0 1;
 O_7SEGDATA5[6] 0x3 0 1;
 O_7SEGDATA5[7] 0x3 0 1;
 O_7SEGDATA6[0] 0x3 0 0;
 O_7SEGDATA6[1] 0x3 0 0;
 O_7SEGDATA6[2] 0x3 0 1;
 O_7SEGDATA6[3] 0x3 0 1;
 O_7SEGDATA6[4] 0x3 0 1;
 O_7SEGDATA6[5] 0x3 0 1;
 O_7SEGDATA6[6] 0x3 0 1;
 O_7SEGDATA6[7] 0x3 0 1;
 O_7SEGDATA7[0] 0x3 0 0;
 O_7SEGDATA7[1] 0x3 0 0;
 O_7SEGDATA7[2] 0x3 0 1;
 O_7SEGDATA7[3] 0x3 0 1;
 O_7SEGDATA7[4] 0x3 0 1;
 O_7SEGDATA7[5] 0x3 0 1;
 O_7SEGDATA7[6] 0x3 0 1;
 O_7SEGDATA7[7] 0x3 0 1;
 O_7SEGDATA8[0] 0x3 0 0;
 O_7SEGDATA8[1] 0x3 0 1;
 O_7SEGDATA8[2] 0x3 0 0;
 O_7SEGDATA8[3] 0x3 0 1;
 O_7SEGDATA8[4] 0x3 0 1;
 O_7SEGDATA8[5] 0x3 0 0;
 O_7SEGDATA8[6] 0x3 0 1;
 O_7SEGDATA8[7] 0x3 0 1;
 O_ADR_V[0] 0x3 233.333 0.286666;
 O_ADR_V[1] 0x3 166.667 0.686666;
 O_ADR_V[2] 0x3 233.333 0.24;
 O_ADR_V[3] 0x3 366.667 0.506666;
 O_ADR_V[4] 0x3 366.667 0.506666;
 O_ADR_V[5] 0x3 366.667 0.506666;
 O_ADR_V[6] 0x3 366.667 0.506666;
 O_ADR_V[7] 0x3 100 0.906666;
 O_ALUDATA_V[0] 0x3 366.667 0.593333;
 O_ALUDATA_V[1] 0x3 666.667 0.54;
 O_ALUDATA_V[2] 0x3 266.667 0.233333;
 O_ALUDATA_V[3] 0x3 66.6667 1.22333e-008;
 O_ALUDATA_V[4] 0x3 0 0;
 O_ALUDATA_V[5] 0x3 133.333 0.133333;
 O_ALUDATA_V[6] 0x3 66.6667 0.0666667;
 O_ALUDATA_V[7] 0x3 433.333 0.433333;
 O_ALUDATA_V[8] 0x3 333.333 0.286667;
 O_ALUDATA_V[9] 0x3 266.667 0.06;
 O_ALUDATA_V[10] 0x3 66.6667 1.01333e-008;
 O_ALUDATA_V[11] 0x3 0 0;
 O_ALUDATA_V[12] 0x3 0 0;
 O_ALUDATA_V[13] 0x3 0 0;
 O_ALUDATA_V[14] 0x3 0 0;
 O_ALUDATA_V[15] 0x3 0 0;
 O_AX_V[0] 0x3 0 1;
 O_AX_V[1] 0x3 0 0;
 O_AX_V[2] 0x3 0 0;
 O_AX_V[3] 0x3 0 0;
 O_AX_V[4] 0x3 0 0;
 O_AX_V[5] 0x3 0 0;
 O_AX_V[6] 0x3 0 0;
 O_AX_V[7] 0x3 0 1;
 O_AX_V[8] 0x3 0 1;
 O_AX_V[9] 0x3 0 1;
 O_AX_V[10] 0x3 0 0;
 O_AX_V[11] 0x3 0 0;
 O_AX_V[12] 0x3 0 0;
 O_AX_V[13] 0x3 0 0;
 O_AX_V[14] 0x3 0 0;
 O_AX_V[15] 0x3 0 1;
 O_BCUEXTBUS_V[0] 0x3 133.333 0.0266666;
 O_BCUEXTBUS_V[1] 0x3 600 0.186667;
 O_BCUEXTBUS_V[2] 0x3 933.333 0.28;
 O_BCUEXTBUS_V[3] 0x3 266.667 0.133333;
 O_BCUEXTBUS_V[4] 0x3 533.333 0.266667;
 O_BCUEXTBUS_V[5] 0x3 533.333 0.266667;
 O_BCUEXTBUS_V[6] 0x3 533.333 0.266667;
 O_BCUEXTBUS_V[7] 0x3 666.667 0.293333;
 O_BCUEXTBUS_V[8] 0x3 1133.33 0.413333;
 O_BCUEXTBUS_V[9] 0x3 1133.33 0.386666;
 O_BCUEXTBUS_V[10] 0x3 866.667 0.266667;
 O_BCUEXTBUS_V[11] 0x3 866.667 0.266667;
 O_BCUEXTBUS_V[12] 0x3 533.333 0.266666;
 O_BCUEXTBUS_V[13] 0x3 800 0.266666;
 O_BCUEXTBUS_V[14] 0x3 533.333 0.266666;
 O_BCUEXTBUS_V[15] 0x3 800 0.266666;
 O_BCUSTATE_V[0] 0x3 1800 0.18;
 O_BCUSTATE_V[1] 0x3 1000 0.18;
 O_BCUSTATE_V[2] 0x3 200 0.0599997;
 O_BDATA[0] 0x3 66.6667 4.33333e-008;
 O_BDATA[1] 0x3 200 5.26e-008;
 O_BDATA[2] 0x3 333.333 0.04;
 O_BDATA[3] 0x3 0 0;
 O_BDATA[4] 0x3 133.333 2.07333e-008;
 O_BDATA[5] 0x3 333.333 0.0400001;
 O_BDATA[6] 0x3 200 0.04;
 O_BDATA[7] 0x3 200 7e-008;
 O_BP_V[0] 0x3 0 1;
 O_BP_V[1] 0x3 0 1;
 O_BP_V[2] 0x3 0 0;
 O_BP_V[3] 0x3 0 0;
 O_BP_V[4] 0x3 0 0;
 O_BP_V[5] 0x3 0 0;
 O_BP_V[6] 0x3 0 0;
 O_BP_V[7] 0x3 0 0;
 O_BP_V[8] 0x3 0 0;
 O_BP_V[9] 0x3 0 0;
 O_BP_V[10] 0x3 0 0;
 O_BP_V[11] 0x3 0 0;
 O_BP_V[12] 0x3 0 0;
 O_BP_V[13] 0x3 0 0;
 O_BP_V[14] 0x3 0 0;
 O_BP_V[15] 0x3 0 0;
 O_BX_V[0] 0x3 0 1;
 O_BX_V[1] 0x3 0 0;
 O_BX_V[2] 0x3 0 0;
 O_BX_V[3] 0x3 0 0;
 O_BX_V[4] 0x3 0 0;
 O_BX_V[5] 0x3 0 0;
 O_BX_V[6] 0x3 0 0;
 O_BX_V[7] 0x3 0 0;
 O_BX_V[8] 0x3 0 1;
 O_BX_V[9] 0x3 0 1;
 O_BX_V[10] 0x3 0 0;
 O_BX_V[11] 0x3 0 0;
 O_BX_V[12] 0x3 0 0;
 O_BX_V[13] 0x3 0 0;
 O_BX_V[14] 0x3 0 0;
 O_BX_V[15] 0x3 0 0;
 O_CS_V[0] 0x3 0 1;
 O_CS_V[1] 0x3 0 1;
 O_CS_V[2] 0x3 0 1;
 O_CS_V[3] 0x3 0 1;
 O_CS_V[4] 0x3 0 1;
 O_CS_V[5] 0x3 0 1;
 O_CS_V[6] 0x3 0 1;
 O_CS_V[7] 0x3 0 1;
 O_CS_V[8] 0x3 0 1;
 O_CS_V[9] 0x3 0 1;
 O_CS_V[10] 0x3 0 1;