inbus.vhd

X8086的VHDL源码

library IEEE; 
use IEEE.STD_LOGIC_1164.all;
use WORK.UPAC.ALL;

entity INBUS is
	port( I_BUSCS	 :  in std_logic_vector ( 4 downto 0);
		  I_TREG1    :  in std_logic_vector (15 downto 0);
      	  I_TREG2    :  in std_logic_vector (15 downto 0);
          I_GREG 	 :  in std_logic_vector (15 downto 0);
          I_ALUDATA  :  in std_logic_vector (15 downto 0);
          I_BIUDATA  :  in std_logic_vector (15 downto 0);
          I_FREG	 :  in std_logic_vector ( 8 downto 0);
          O_TREG1    : out std_logic_vector (15 downto 0);
	      O_TREG2    : out std_logic_vector (15 downto 0);
	      O_GREG     : out std_logic_vector (15 downto 0);
          O_EUDATA     : out std_logic_vector (15 downto 0);
          O_FREG     : out std_logic_vector ( 8 downto 0)
		  );
end;

architecture RTL of INBUS is
begin

	GREG_OUT : 
	process(I_BUSCS,I_BIUDATA,I_FREG,I_ALUDATA,I_TREG1,I_TREG2)
	begin
		if    (I_BUSCS = B2G) then
			O_GREG <= I_BIUDATA;
		elsif (I_BUSCS = F2G) then
			O_GREG <= "XXXX"&I_FREG(8 downto 5)&I_FREG(4 downto 3)&'X'&I_FREG(2)&'X'&I_FREG(1)&'X'&I_FREG(0);
 	    elsif (I_BUSCS = A2G) then
			O_GREG <= I_ALUDATA;
		elsif (I_BUSCS = T12G) then
			O_GREG <= I_TREG1;
		elsif (I_BUSCS = T22G) then
			O_GREG <= I_TREG2;
		elsif (I_BUSCS = "11111") then 
			O_GREG <= I_ALUDATA;
		else
			O_GREG <= "ZZZZZZZZZZZZZZZZ";
		end if;
	end process;

	BIU_OUT : 
	process(I_BUSCS,I_GREG,I_FREG,I_ALUDATA,I_TREG1,I_TREG2)
	begin
		if    (I_BUSCS = G2B) then
			O_EUDATA <= I_GREG;
		elsif (I_BUSCS = F2B) then
			O_EUDATA <= "XXXX"&I_FREG(8 downto 5)&I_FREG(4 downto 3)&'X'&I_FREG(2)&'X'&I_FREG(1)&'X'&I_FREG(0);
		elsif (I_BUSCS = A2B) then
			O_EUDATA <= I_ALUDATA;
		elsif (I_BUSCS = T12B) then
			O_EUDATA <= I_TREG1;
		elsif (I_BUSCS = T22B) then
			O_EUDATA <= I_TREG2;
		elsif (I_BUSCS = "11111") then 
			O_EUDATA <= I_ALUDATA;
		else
			O_EUDATA <= "----------------";
		end if;
	end process;

	FREG_OUT : 
	process(I_BUSCS,I_GREG,I_BIUDATA)
	begin
		if    (I_BUSCS = G2F) then
			O_FREG <= I_GREG(11 downto 6)&I_GREG(4)&I_GREG(2)&I_GREG(0);
		elsif (I_BUSCS = B2F) then
			O_FREG <= I_BIUDATA(11 downto 6)&I_BIUDATA(4)&I_BIUDATA(2)&I_BIUDATA(0);
		else
			O_FREG <= "XXXXXXXXX";
		end if;
	end process;

	TREG1_OUT : 
	process(I_BUSCS,I_GREG,I_BIUDATA,I_ALUDATA)
	begin
		if    (I_BUSCS = G2T1)then
			O_TREG1 <= I_GREG;
		elsif (I_BUSCS = B2T1) then
			O_TREG1 <= I_BIUDATA;
		elsif (I_BUSCS = A2T1) then
			O_TREG1 <= I_ALUDATA;
		else
			O_TREG1 <= "ZZZZZZZZZZZZZZZZ";
		end if;
	end process;

	TREG2_OUT : 
	process(I_BUSCS,I_GREG,I_BIUDATA,I_ALUDATA,I_TREG1)
	begin
		if    (I_BUSCS = G2T2)then
			O_TREG2 <= I_GREG;
		elsif (I_BUSCS = B2T2) then
			O_TREG2 <= I_BIUDATA;
		elsif (I_BUSCS = T12T2) then
			O_TREG2 <= I_TREG1;
		elsif (I_BUSCS = A2T2) then
			O_TREG2 <= I_ALUDATA;
		else
			O_TREG2 <= "ZZZZZZZZZZZZZZZZ";
		end if;
	end process;

end;