cque.vhd

X8086的VHDL源码

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--   FILE NAME : C_QUE_FETCH.vhd
--   FUNCTION  : QUE Control Unit
--   AUTHOR    : Kazuma Mishima
--   DATE      : 6/2001
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.UPAC.all;

entity CQUE is
    port( I_CLK     :  in std_logic;
          I_RST     :  in std_logic;
		  I_EUCRST  :  in std_logic; --from EUC reset signal
          I_DATA    :  in std_logic_vector(15 downto 0); --IN DATA form DC
          I_QUEF    :  in std_logic; --DATA out flag from DC
		  I_ODD     :  in std_logic; --I_ADR(0)='1'(odd) => '1'
		  O_QUEWR_N : out std_logic; --negative write signal to QUE
		  O_CQUEF   : out std_logic; --write QUE =>> '1'
          O_BDATA   : out std_logic_vector( 7 downto 0) --DATA out to QUE
		  ); 
end CQUE;

architecture RTL of CQUE is

type   STATE is (S0,So1,Se1,Se2);
signal current_state : STATE;
signal next_state    : STATE;
signal op            : std_logic_vector(7 downto 0); --data ratch

begin
--NEXT STATE 
	CQUE_CURRENTSTATE : 
	process(I_CLK,I_RST,I_EUCRST,next_state)
	begin 
		if (I_RST = RST_ACT) then
			current_state <= S0;
		elsif (I_CLK'event and I_CLK = '0') then
			if (I_EUCRST = '1')then
				current_state <= S0;
			else
				current_state <= next_state;
			end if;
		end if;
	end process;

	OP_REG : 
	process(I_CLK,I_RST,current_state,I_DATA)
	begin
		if (I_RST = RST_ACT) then
			op <= "00000000";
		elsif (I_CLK'event and I_CLK = '0') then
			if    (current_state = S0) then
				op <= "00000000";
			elsif (current_state = Se1) then
				op <= I_DATA(15 downto 8);
			end if;
		end if;
	end process;

--write fifo
	process(current_state,I_DATA,op)
	begin
		case current_state is
		when S0 => 
			O_QUEWR_N <= '1'; --not write
			O_CQUEF   <= '0';
			O_BDATA   <= (others => '0');
		when So1 => 
			O_QUEWR_N <= '0';
			O_BDATA   <= I_DATA( 7 downto 0);
			O_CQUEF   <= '1';
		when Se1 => 
			O_QUEWR_N <= '0';
			O_BDATA   <= I_DATA( 7 downto 0);
			O_CQUEF   <= '0';
		when Se2 => 
			O_QUEWR_N <= '0';
			O_BDATA   <= op;
			O_CQUEF   <= '1';
		when others =>
			O_QUEWR_N <= 'X';
			O_BDATA   <= "XXXXXXXX";
			O_CQUEF   <= 'X';
		end case;
	end process;

--FSM    
	process(current_state,I_QUEF,I_ODD) 
	begin
		case current_state is
		when S0 => 
			if    (I_QUEF='1' and I_ODD='1')then --first write,odd
				next_state <= So1;
			elsif (I_QUEF='1' and I_ODD='0')then --even
				next_state <= Se1;
			else
				next_state <= S0;
			end if;
		when So1 => 
			next_state <= S0;
		when Se1 => 
			next_state <= Se2;
		when Se2 => 
			next_state <= S0; --second write,even
		when others => 
			next_state <= S0;
		end case;
	end process;

end RTL;