📄 upac.vhd
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constant AFR : integer := 2;
constant PFR : integer := 1;
constant CFR : integer := 0;
--instruction(OPcode) -- Instruction start
constant MOV : std_logic_vector(5 downto 0) := "100010";
--MOV:戞侾僆儁儔儞僪 斈梡儗僕僗僞丂戞俀僆儁儔儞僪丂斈梡儗僕僗僞
--MOV:戞俀僆儁儔儞僪偺撪梕傪戞侾僆儁儔儞僪傊揮憲偡傞丅
--MOV:巊梡椺丗MOV AX,CX
constant MOVi : std_logic_vector(6 downto 0) := "1100011";
--MOVi:戞俀僆儁儔儞僪偺撪梕傪戞侾僆儁儔儞僪傊揮憲偡傞
constant MOVireg : std_logic_vector(3 downto 0) := "1011";
constant MOVma : std_logic_vector(6 downto 0) := "1010000";
constant MOVam : std_logic_vector(6 downto 0) := "1010001";
constant MOVrms : std_logic_vector(7 downto 0) := "10001110";
constant MOVsrm : std_logic_vector(7 downto 0) := "10001100";
constant PUSH : std_logic_vector(7 downto 0) := "11111111";
-- constant POP : std_logic_vector(7 downto 0) := "10001111";
-- constant POPreg : std_logic_vector(4 downto 0) := "01011";
-- constant XCHG : std_logic_vector(6 downto 0) := "1000011";
-- constant XCHGax : std_logic_vector(4 downto 0) := "10010";
-- constant INN : std_logic_vector(6 downto 0) := "1110010";
-- constant INdx : std_logic_vector(6 downto 0) := "1110110";
-- constant OUTT : std_logic_vector(6 downto 0) := "1110011";
-- constant OUTdx : std_logic_vector(6 downto 0) := "1110111";
-- constant XLAT : std_logic_vector(7 downto 0) := "11010111";
-- constant LEA : std_logic_vector(7 downto 0) := "10001101";
-- constant LDSES : std_logic_vector(6 downto 0) := "1100010";
constant PUSHF : std_logic_vector(7 downto 0) := "10011100";
constant POPF : std_logic_vector(7 downto 0) := "10011101";
constant LAHF : std_logic_vector(7 downto 0) := "10011111";
constant SAHF : std_logic_vector(7 downto 0) := "10011110";
--aritmetic
constant ADD : std_logic_vector(5 downto 0) := "000000";
constant Imm2EA : std_logic_vector(5 downto 0) := "100000";
constant ADDia : std_logic_vector(6 downto 0) := "0000010";
constant ADC : std_logic_vector(5 downto 0) := "000100";
constant ADCia : std_logic_vector(6 downto 0) := "0001010";
-- constant INCDEC : std_logic_vector(6 downto 0) := "1111111";
-- constant INCreg : std_logic_vector(4 downto 0) := "01000";
-- constant DECreg : std_logic_vector(4 downto 0) := "01001";
constant AAA : std_logic_vector(7 downto 0) := "00110111";
constant DAA : std_logic_vector(7 downto 0) := "00100111";
-- constant SUBre : std_logic_vector(5 downto 0) := "001010";
-- constant SUBia : std_logic_vector(6 downto 0) := "0010110";
-- constant SBB : std_logic_vector(5 downto 0) := "000110";
-- constant SBBia : std_logic_vector(6 downto 0) := "0001110";
-- constant CMP : std_logic_vector(5 downto 0) := "001110";
-- constant CMPia : std_logic_vector(6 downto 0) := "0011110";
constant AAS : std_logic_vector(7 downto 0) := "00111111";
constant DAS : std_logic_vector(7 downto 0) := "00101111";
constant AAM : std_logic_vector(7 downto 0) := "11010100";
constant AAD : std_logic_vector(7 downto 0) := "11010101";
constant CBW : std_logic_vector(7 downto 0) := "10011000";
constant CWD : std_logic_vector(7 downto 0) := "10011001";
constant CALL : std_logic_vector(7 downto 0) := "11101000";
constant CALLdi : std_logic_vector(7 downto 0) := "10011010";
constant JMP : std_logic_vector(7 downto 0) := "11101001";
constant JMPdw : std_logic_vector(7 downto 0) := "11101011";
constant JMPdi : std_logic_vector(7 downto 0) := "11101010";
-- constant RET : std_logic_vector(7 downto 0) := "11000011";
-- constant RETwa : std_logic_vector(7 downto 0) := "11000010";
-- constant RETi : std_logic_vector(7 downto 0) := "11001011";
-- constant RETia : std_logic_vector(7 downto 0) := "11001010";
constant DNT : std_logic_vector(6 downto 0) := "1111011";
--LOGIC
constant SHIFT : std_logic_vector(5 downto 0) := "110100";
constant ANDO : std_logic_vector(5 downto 0) := "001000";
constant TEST : std_logic_vector(6 downto 0) := "1000010";
constant ORR : std_logic_vector(5 downto 0) := "000010";
-- constant XORR : std_logic_vector(5 downto 0) := "001100";
-- constant ANDia : std_logic_vector(6 downto 0) := "0010010";
-- constant ORia : std_logic_vector(6 downto 0) := "0000110";
-- constant XORia : std_logic_vector(6 downto 0) := "0011010";
constant TESTia : std_logic_vector(6 downto 0) := "1010100";
--STRING MANIPULATION
-- constant REP : std_logic_vector(6 downto 0) := "1111001";
-- constant MOVS : std_logic_vector(6 downto 0) := "1010010";
-- constant CMPS : std_logic_vector(6 downto 0) := "1010011";
constant SCAS : std_logic_vector(6 downto 0) := "1010111";
constant LODS : std_logic_vector(6 downto 0) := "1010110";
constant STOS : std_logic_vector(6 downto 0) := "1010101";
--CONTROL TRANSFER
constant JE : std_logic_vector(7 downto 0) := "01110100";
constant JL : std_logic_vector(7 downto 0) := "01111100";
constant JLE : std_logic_vector(7 downto 0) := "01111110";
constant JB : std_logic_vector(7 downto 0) := "01110010";
constant JBE : std_logic_vector(7 downto 0) := "01110110";
-- constant JP : std_logic_vector(7 downto 0) := "01111010";
-- constant JO : std_logic_vector(7 downto 0) := "01110000";
-- constant JS : std_logic_vector(7 downto 0) := "01111000";
-- constant JNE : std_logic_vector(7 downto 0) := "01110101";
-- constant JNL : std_logic_vector(7 downto 0) := "01111101";
-- constant JNLE : std_logic_vector(7 downto 0) := "01111111";
--- constant JNB : std_logic_vector(7 downto 0) := "01110011";
-- constant JNBE : std_logic_vector(7 downto 0) := "01110111";
constant JNP : std_logic_vector(7 downto 0) := "01111011";
constant JNO : std_logic_vector(7 downto 0) := "01110001";
constant JNS : std_logic_vector(7 downto 0) := "01111001";
-- constant LOP : std_logic_vector(7 downto 0) := "11100010";
-- constant LOPZ : std_logic_vector(7 downto 0) := "11100001";
-- constant LOPNZ : std_logic_vector(7 downto 0) := "11100000";
constant JCXZ : std_logic_vector(7 downto 0) := "11100011";
constant INT : std_logic_vector(7 downto 0) := "11001101";
constant INT_3 : std_logic_vector(7 downto 0) := "11001100";
constant INTO : std_logic_vector(7 downto 0) := "11001110";
constant IRET : std_logic_vector(7 downto 0) := "11001111";
--PROCESSOR CONTROL
-- constant CLC : std_logic_vector(7 downto 0) := "11111000";
-- constant CMC : std_logic_vector(7 downto 0) := "11110101";
-- constant STC : std_logic_vector(7 downto 0) := "11111001";
-- constant CLD : std_logic_vector(7 downto 0) := "11111100";
-- constant STDD : std_logic_vector(7 downto 0) := "11111101";
constant CLI : std_logic_vector(7 downto 0) := "11111010";
constant STI : std_logic_vector(7 downto 0) := "11111011";
constant HLT : std_logic_vector(7 downto 0) := "11110100";
-- Instruction end
--ALU
constant GEN : std_logic_vector(3 downto 0) := "0000"; --substruct
constant KA : std_logic_vector(3 downto 0) := "0001"; --add
constant JOU : std_logic_vector(3 downto 0) := "0010"; --add(to multiple)
constant NO : std_logic_vector(3 downto 0) := "0011"; --NOT
constant KATU : std_logic_vector(3 downto 0) := "0100"; --AND
constant MATA : std_logic_vector(3 downto 0) := "0101"; --OR
constant HAI : std_logic_vector(3 downto 0) := "0110"; --XOR
constant HSIF : std_logic_vector(3 downto 0) := "1000"; --right shift
constant RMSIF : std_logic_vector(3 downto 0) := "1001"; --logical left shift
constant SMSIF : std_logic_vector(3 downto 0) := "1010"; --arithmetic left shift
constant HRO : std_logic_vector(3 downto 0) := "1011"; --left rotate
constant MRO : std_logic_vector(3 downto 0) := "1100"; --right rotate
constant CHRO : std_logic_vector(3 downto 0) := "1101"; --left rotate with carry
constant CMRO : std_logic_vector(3 downto 0) := "1110"; --right rorate with carry
constant ALUNEG : std_logic_vector(3 downto 0) := "1111"; --twos complement conversion
--BUS_SET
constant G2B : std_logic_vector(4 downto 0) := "00100"; --GR to BIU
constant F2B : std_logic_vector(4 downto 0) := "00101"; --FR to BIU
constant A2B : std_logic_vector(4 downto 0) := "00110"; --ALU to BIU
constant T22B : std_logic_vector(4 downto 0) := "00111"; --TMP2 to BIU
constant B2G : std_logic_vector(4 downto 0) := "01000"; --BIU to GR
constant F2G : std_logic_vector(4 downto 0) := "01001"; --FR to GR
constant A2G : std_logic_vector(4 downto 0) := "01010"; --ALU to GR
constant T12G : std_logic_vector(4 downto 0) := "01100"; --TMP1 to GR
constant T22G : std_logic_vector(4 downto 0) := "01101"; --TMP2 to GR
constant G2F : std_logic_vector(4 downto 0) := "10000"; --GR to FR
constant B2F : std_logic_vector(4 downto 0) := "10001"; --BIU to FR
constant G2T1 : std_logic_vector(4 downto 0) := "11000"; --GR to TMP1
constant B2T1 : std_logic_vector(4 downto 0) := "11001"; --BIU to TMP1
constant A2T1 : std_logic_vector(4 downto 0) := "11010"; --ALU to TMP1
constant G2T2 : std_logic_vector(4 downto 0) := "11100"; --GR to TMP2
constant B2T2 : std_logic_vector(4 downto 0) := "11101"; --BIU to TMP2
constant A2T2 : std_logic_vector(4 downto 0) := "11110"; --ALU to TMP2
constant T12B : std_logic_vector(4 downto 0) := "00011"; --TMP1 to BIU
constant T12T2 : std_logic_vector(4 downto 0) := "11011"; --TMP1 to TMP2
--register select
constant AL : std_logic_vector(3 downto 0) := "0000";
constant CL : std_logic_vector(3 downto 0) := "0001";
constant DL : std_logic_vector(3 downto 0) := "0010";
constant BL : std_logic_vector(3 downto 0) := "0011";
constant AH : std_logic_vector(3 downto 0) := "0100";
constant CH : std_logic_vector(3 downto 0) := "0101";
constant DH : std_logic_vector(3 downto 0) := "0110";
constant BH : std_logic_vector(3 downto 0) := "0111";
constant AX : std_logic_vector(3 downto 0) := "1000";
constant CX : std_logic_vector(3 downto 0) := "1001";
constant DX : std_logic_vector(3 downto 0) := "1010";
constant BX : std_logic_vector(3 downto 0) := "1011";
constant SP : std_logic_vector(3 downto 0) := "1100";
constant BP : std_logic_vector(3 downto 0) := "1101";
constant SIX : std_logic_vector(3 downto 0) := "1110";
constant DIX : std_logic_vector(3 downto 0) := "1111";
end UPAC;⌨️ 快捷键说明
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