fr.vhd

X8086的VHDL源码

library ieee;
use ieee.STD_LOGIC_1164.all;
library synplify;
use synplify.attributes.all;
 
entity FR is
	port( I_CLK   :  in std_logic;
          I_RST   :  in std_logic;
          I_STFR  :  in std_logic_vector( 5 downto 0 );
          I_FRSEL :  in std_logic;
          I_FREN  :  in std_logic_vector(17 downto 0 );
          I_FREG  :  in std_logic_vector( 8 downto 0 );
		  O_CFR   : out std_logic;
		  O_AFR   : out std_logic;
          O_FREG  : out std_logic_vector( 8 downto 0 )
          ); 
end FR;
 
architecture RTL of FR is
 
signal FRJ_FREG : std_logic_vector( 8 downto 0 );

component MPX2IN1OUTB
    port( I_SW :  in std_logic;
		  I_DATA01  :  in std_logic_vector( 5 downto 0);      
		  I_DATA11  :  in std_logic_vector( 8 downto 0);
          O_DATA    : out std_logic_vector( 8 downto 0)
		  );
end component;

component FREG
    port( I_CLK  :  in std_logic;
          I_RST  :  in std_logic;
		  I_FREG :  in std_logic_vector( 8 downto 0);
		  I_FREN :  in std_logic_vector(17 downto 0);
		  O_CFR  : out std_logic;
		  O_AFR  : out std_logic;
          O_FREG : out std_logic_vector( 8 downto 0)
		  );
end component; 

begin
 
	MPX2IN1OUTB_FR : MPX2IN1OUTB
    port map( 
		I_SW => I_FRSEL,
		I_DATA01 => I_STFR,
		I_DATA11 => I_FREG,
        O_DATA => FRJ_FREG
		);

	FREG_FR : FREG
    port map( 
		I_CLK => I_CLK,
        I_RST => I_RST,
		I_FREG => FRJ_FREG,
		I_FREN => I_FREN,
		O_CFR => O_CFR,
		O_AFR => O_AFR,
        O_FREG => O_FREG
		);

end RTL;