biu.vhd

来自「X8086的VHDL源码」· VHDL 代码 · 共 367 行

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library synplify;
use synplify.attributes.all;
  
entity BIU is
	port( I_CLK        :  in std_logic;
          I_RST        :  in std_logic;
          I_RDY        :  in std_logic;
          I_MOD        :  in std_logic_vector( 1 downto 0 );
          I_BW         :  in std_logic;
          I_RM         :  in std_logic_vector( 2 downto 0 );
          I_CSR        :  in std_logic;
          I_SRSEL      :  in std_logic_vector( 1 downto 0 );
          I_EUDATA     :  in std_logic_vector(15 downto 0 );
          I_EARQ       :  in std_logic;
          I_RDQUE      :  in std_logic;
          I_RD         :  in std_logic;
          I_WR         :  in std_logic;
          I_WRIP       :  in std_logic;
          I_WRSR       :  in std_logic;
          I_EAPLUS2    :  in std_logic;
          I_2SR        :  in std_logic;
          I_OADR       :  in std_logic_vector(15 downto 0 );
          I_ADROUT     :  in std_logic;
          I_EUCDATA    :  in std_logic_vector(15 downto 0 );
          I_HLT        :  in std_logic;
          I_IO         :  in std_logic;
          I_MDTF       :  in std_logic;
          I_NFE        :  in std_logic;
          I_PLUSMOD    :  in std_logic_vector( 1 downto 0 );
          I_PLUSOP     :  in std_logic_vector( 2 downto 0 );
          I_QUERST     :  in std_logic;
          I_RDIR       :  in std_logic;
          I_EUCRST     :  in std_logic;
          I_2BIU       :  in std_logic;
          I_2EU        :  in std_logic;
          I_ORPCSR     :  in std_logic;
          I_ORPSRSEL   :  in std_logic_vector( 1 downto 0 );
          I_RDSR       :  in std_logic;
          I_WRIR       :  in std_logic;
          I_WRPLUS     :  in std_logic;
          I_EXTBUS     :  in std_logic_vector(15 downto 0 );
          O_CS_V       : out std_logic_vector(15 downto 0 );
          O_DS_V       : out std_logic_vector(15 downto 0 );
          O_ES_V       : out std_logic_vector(15 downto 0 );
          O_SS_V       : out std_logic_vector(15 downto 0 );
          O_BCUSTATE_V : out std_logic_vector( 2 downto 0 );
		  O_DCSTATE_V  : out std_logic_vector( 3 downto 0 );
          O_DEN_N      : out std_logic;
          O_DTR        : out std_logic;
          O_QUEEMPTY   : out std_logic;
          O_QUEFULL    : out std_logic;
		  O_ALE        : out std_logic;
          O_BHE        : out std_logic;
          O_NOP_V      : out std_logic;
          O_A19A16     : out std_logic_vector( 3 downto 0 );
          O_EXTBUS     : out std_logic_vector(15 downto 0 );
          O_ENDRC      : out std_logic;
          O_ENDWC      : out std_logic;
          O_IO         : out std_logic;
          O_BDATA      : out std_logic_vector( 7 downto 0 );
          O_BIUDATA    : out std_logic_vector(15 downto 0 );
          O_NEXTIP     : out std_logic_vector(15 downto 0 );
          O_RD_N       : out std_logic;
          O_WR_N       : out std_logic 
		  );
end BIU;
  
architecture RTL of BIU is
 
signal FIFO_FE        : std_logic;
signal ADDADR_ADR20   : std_logic_vector(19 downto 0 );
signal DC_RCF         : std_logic;
signal DC_DATA2EU     : std_logic_vector(15 downto 0 );
signal DC_DATA2QUE    : std_logic_vector(15 downto 0 );
signal DC_WCF         : std_logic;
signal DC_ODD         : std_logic;
signal DC_QUEF        : std_logic;
signal DTMPX_DATA2MEM : std_logic_vector(15 downto 0 );
signal DTMPX_DATA2SR  : std_logic_vector(15 downto 0 );
signal FIFO_WRQUE     : std_logic;
signal IP_IPF         : std_logic;
signal IPIRMPX_DATA   : std_logic_vector(15 downto 0 );
signal IR_IRF         : std_logic;
signal IR_DATA        : std_logic_vector(15 downto 0 );
signal EUSRMPX_DATA   : std_logic_vector(15 downto 0 );
signal REGST_DATA     : std_logic_vector(15 downto 0 );

component ADDADR
	generic( SRW   : integer;
	         IRW   : integer;
			 PADRW : integer
			 );
    port( I_SREGDATA :  in std_logic_vector(SRW-1 downto 0); --input segment data
          I_IPIRDATA :  in std_logic_vector(IRW-1 downto 0); --input IP or IR 
		  I_EAPLUS2  :  in std_logic ; -- '1' => EA+2	
		  O_PADR     : out std_logic_vector(PADRW-1 downto 0)  --OUT Adress(20bit)
		   );                    		  
end component;

component BCU
	port( I_CLK        :  in std_logic;
          I_RST        :  in std_logic;	
          I_RDY        :  in std_logic;	  
          I_RD         :  in std_logic;
          I_BW         :  in std_logic;
          I_WR         :  in std_logic;
          I_ADROUT     :  in std_logic;
          I_IO         :  in std_logic;
          I_EUCRST     :  in std_logic;
          I_FE         :  in std_logic;
          I_IPF        :  in std_logic;
          I_IRF        :  in std_logic;
          I_OADR       :  in std_logic_vector(15 downto 0 );
          I_PADR       :  in std_logic_vector(19 downto 0 );
          I_DATA2MEM   :  in std_logic_vector(15 downto 0 );
          I_EXTBUS     :  in std_logic_vector(15 downto 0 );
          O_ENDRC      : out std_logic;
          O_ENDWC      : out std_logic;
          O_IO         : out std_logic;
          O_ODD        : out std_logic;
          O_QUEF       : out std_logic;
          O_BHE        : out std_logic;
          O_DATA2EU    : out std_logic_vector(15 downto 0 );
          O_DATA2QUE   : out std_logic_vector(15 downto 0 );
          O_DEN_N      : out std_logic;
          O_DTR        : out std_logic;
          O_RD_N       : out std_logic;
		  O_ALE        : out std_logic;
          O_WR_N       : out std_logic;
          O_BCUSTATE_V : out std_logic_vector( 2 downto 0 );
		  O_DCSTATE_V  : out std_logic_vector( 3 downto 0 );
          O_A19A16     : out std_logic_vector( 3 downto 0 );
          O_EXTBUS     : out std_logic_vector(15 downto 0 )
		  ); 
end component;
						
component FETCH
	port( I_CLK      :  in std_logic;
          I_RST      :  in std_logic;
          I_RDQUE    :  in std_logic;
          I_DATA     :  in std_logic_vector(15 downto 0 );
          I_ODD      :  in std_logic;
          I_QUEF     :  in std_logic;
          I_QUERST   :  in std_logic;
          I_EUCRST   :  in std_logic;
          O_BDATA    : out std_logic_vector(7 downto 0 );
          O_FE       : out std_logic;
          O_CQUEF    : out std_logic;
          O_QUEEMPTY : out std_logic;
          O_QUEFULL  : out std_logic
          ); 
end component;

component SRIR
	port( I_CLK      :  in std_logic;
          I_RST      :  in std_logic;
          I_MOD      :  in std_logic_vector( 1 downto 0 );
          I_RM       :  in std_logic_vector( 2 downto 0 );
          I_NFE      :  in std_logic;
          I_RD       :  in std_logic;
          I_WR       :  in std_logic;
          I_WRIP     :  in std_logic;
          I_WRIR     :  in std_logic;
          I_RDSR     :  in std_logic;
          I_WRSR     :  in std_logic;
          I_WRPLUS   :  in std_logic;
          I_HLT      :  in std_logic;
          I_MDTF     :  in std_logic;
          I_PLUSMOD  :  in std_logic_vector( 1 downto 0 );
          I_PLUSOP   :  in std_logic_vector( 2 downto 0 );
          I_EUCRST   :  in std_logic;
          I_CSR      :  in std_logic;
          I_ORPCSR   :  in std_logic;
          I_SRSEL    :  in std_logic_vector( 1 downto 0 );
          I_ORPSRSEL :  in std_logic_vector( 1 downto 0 );
          I_EARQ     :  in std_logic;
          I_WRQUE    :  in std_logic;
          I_FE       :  in std_logic;
          I_ENDRC    :  in std_logic;
          I_ENDWC    :  in std_logic;
          I_EUDATA   :  in std_logic_vector(15 downto 0 );
          I_BIUDATA  :  in std_logic_vector(15 downto 0 );
          O_NOP_V    : out std_logic;
          O_IPF      : out std_logic;
          O_IRF      : out std_logic;
          O_IRDATA   : out std_logic_vector(15 downto 0 );
          O_IPIRDATA : out std_logic_vector(15 downto 0 );
          O_NEXTIP   : out std_logic_vector(15 downto 0 );
          O_SREGDATA : out std_logic_vector(15 downto 0 );
          O_CS_V     : out std_logic_vector(15 downto 0 );
          O_DS_V     : out std_logic_vector(15 downto 0 );
          O_ES_V     : out std_logic_vector(15 downto 0 );
          O_SS_V     : out std_logic_vector(15 downto 0 )
		  ); 
end component;
 
component DTMPX
    port( I_EUDATA   :  in std_logic_vector(15 downto 0 ); --DATA from EA
	      I_WRIP     :  in std_logic; --write signal to IP
		  I_WRIR     :  in std_logic; --write signal to IR
		  I_WRSR     :  in std_logic; --write signal to Segment REGISTAR
		  I_EARQ     :  in std_logic; --EA out => '1'
		  I_EUCDATA  :  in std_logic_vector(15 downto 0 ); --EUC DATA
		  I_2BIU     :  in std_logic; --EUC DATA to BIU signal
		  I_2SR      :  in std_logic; --EUC DATA(address) to Segment Registar
          O_DATA2SR  : out std_logic_vector(15 downto 0 ); --OUTPUT DATA to REGISTAR
          O_DATA2MEM : out std_logic_vector(15 downto 0 ) --OUTPUT DATA to MEMORY
		  );
end component;

component EUSRMPX
    port( I_SREGDATA :  in std_logic_vector(15 downto 0 ); --segment register data
	      I_BCUDATA  :  in std_logic_vector(15 downto 0 ); --BIU data
		  I_IRDATA   :  in std_logic_vector(15 downto 0 ); --IR data
		  I_EUCDATA  :  in std_logic_vector(15 downto 0 ); --EUC data
		  I_2EU      :  in std_logic; --Set EUC data signal 
		  I_RDIR     :  in std_logic; --read IR signal
          I_RDSR     :  in std_logic; --segment register read signal
          O_BIUDATA  : out std_logic_vector(15 downto 0 ) --out data to EU
		  ); 
end component; 

begin
 
	ADDADR_BIU : ADDADR
	generic map(
		SRW => 16,
		IRW => 16,
		PADRW => 20
		)
    port map( 
		I_SREGDATA => REGST_DATA,
        I_IPIRDATA => IPIRMPX_DATA,
		I_EAPLUS2 => I_EAPLUS2,
		O_PADR => ADDADR_ADR20
		);                    		  
 
	T_BCU_BIU : BCU
	port map( 
		I_CLK => I_CLK,
        I_RST => I_RST,
        I_RDY => I_RDY,
        I_RD => I_RD,
        I_BW => I_BW,
        I_WR => I_WR,
        I_ADROUT => I_ADROUT,
        I_IO => I_IO,
        I_EUCRST => I_EUCRST,
        I_FE => FIFO_FE,
        I_IPF => IP_IPF,
        I_IRF => IR_IRF,
        I_OADR => I_OADR,
        I_PADR => ADDADR_ADR20,
        I_DATA2MEM => DTMPX_DATA2MEM,
        I_EXTBUS => I_EXTBUS,
        O_ENDRC => DC_RCF,
        O_ENDWC => DC_WCF,
        O_IO => O_IO,
        O_ODD => DC_ODD,
        O_QUEF => DC_QUEF,
        O_BHE => O_BHE,
        O_DATA2EU => DC_DATA2EU,
        O_DATA2QUE => DC_DATA2QUE,
        O_DEN_N => O_DEN_N,
        O_DTR => O_DTR,
        O_RD_N => O_RD_N,
		O_ALE => O_ALE,
        O_WR_N => O_WR_N,
        O_BCUSTATE_V => O_BCUSTATE_V,
		O_DCSTATE_V => O_DCSTATE_V,
        O_A19A16 => O_A19A16,
        O_EXTBUS => O_EXTBUS
		); 

	T_FETCH_BIU : FETCH
	port map ( 
		I_CLK => I_CLK,
        I_RST => I_RST,
        I_RDQUE => I_RDQUE,  
        I_DATA => DC_DATA2QUE,
        I_ODD => DC_ODD,
        I_QUEF => DC_QUEF,
        I_QUERST => I_QUERST,
        I_EUCRST => I_EUCRST,
        O_BDATA => O_BDATA,
        O_FE => FIFO_FE,
        O_CQUEF => FIFO_WRQUE,
        O_QUEEMPTY => O_QUEEMPTY,
        O_QUEFULL => O_QUEFULL
        ); 

	SRIR_BIU : SRIR
	port map( 
		I_CLK => I_CLK,
        I_RST => I_RST,
        I_MOD => I_MOD,
        I_RM => I_RM,
        I_NFE => I_NFE,
        I_RD => I_RD,
        I_WR => I_WR,
        I_WRIP => I_WRIP,
        I_WRIR => I_WRIR,
        I_RDSR => I_RDSR,
        I_WRSR => I_WRSR,
        I_WRPLUS => I_WRPLUS,
        I_HLT => I_HLT,
        I_MDTF => I_MDTF,
        I_PLUSMOD => I_PLUSMOD,
        I_PLUSOP => I_PLUSOP,
        I_EUCRST => I_EUCRST,
        I_CSR => I_CSR,
        I_ORPCSR => I_ORPCSR,
        I_SRSEL => I_SRSEL,
        I_ORPSRSEL => I_ORPSRSEL,
        I_EARQ => I_EARQ,
        I_WRQUE => FIFO_WRQUE,
        I_FE => FIFO_FE,
        I_ENDRC => DC_RCF,
        I_ENDWC => DC_WCF,
        I_EUDATA => DTMPX_DATA2SR,
        I_BIUDATA => EUSRMPX_DATA,
        O_NOP_V => O_NOP_V,
        O_IPF => IP_IPF,
        O_IRF => IR_IRF,
        O_IRDATA => IR_DATA,
        O_IPIRDATA => IPIRMPX_DATA,
        O_NEXTIP => O_NEXTIP,
        O_SREGDATA => REGST_DATA,
        O_CS_V => O_CS_V,
        O_DS_V => O_DS_V,
        O_ES_V => O_ES_V,
        O_SS_V => O_SS_V
		); 

	DTMPX_BIU : DTMPX
    port map( 
		I_EUDATA => I_EUDATA,
	    I_WRIP => I_WRIP,
		I_WRIR => I_WRIR,
		I_WRSR => I_WRSR,
		I_EARQ => I_EARQ,
		I_EUCDATA => I_EUCDATA,
		I_2BIU => I_2BIU,
		I_2SR => I_2SR,
        O_DATA2SR => DTMPX_DATA2SR,
        O_DATA2MEM => DTMPX_DATA2MEM
		);
 
	EUSRMPX_BIU : EUSRMPX
    port map( 
		I_SREGDATA => REGST_DATA,  
	    I_BCUDATA => DC_DATA2EU,
		I_IRDATA => IR_DATA,
		I_EUCDATA => I_EUCDATA,
		I_2EU => I_2EU,
		I_RDIR => I_RDIR,
        I_RDSR => I_RDSR,
        O_BIUDATA => EUSRMPX_DATA
		); 

	O_BIUDATA  <= EUSRMPX_DATA;
	O_ENDRC    <= DC_RCF;
	O_ENDWC    <= DC_WCF;

end RTL;