nextip.vhd

X8086的VHDL源码

-------------------------------------
--   FILE NAME : NEXT_IP_REG.vhd
--   FUNCTION  : NEXT OP code Instruction pointer
--   AUTHOR    : Kazuma Mishima
--   DATE      : 5/2001
--------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use WORK.UPAC.ALL;

entity NEXTIP is
    port( I_CLK     :  in std_logic;                            
          I_RST     :  in std_logic;
		  I_DATA    :  in std_logic_vector(15 downto 0 ); --input data 
		  I_WRIP    :  in std_logic; --WRITE IP signal
		  I_WRPLUS  :  in std_logic; --plus write signal
          I_PLUSOP  :  in std_logic_vector( 2 downto 0 ); --+1,+2,+3,+4,
		  I_PLUSMOD :  in std_logic_vector( 1 downto 0 ); --+1,+2,
          O_NEXTIP  : out std_logic_vector(15 downto 0 ) --OUT next IP data
		  ); 
end NEXTIP;

architecture RTL of NEXTIP is

signal ip : std_logic_vector(15 downto 0); --IP register

begin
--OUT
	O_NEXTIP <= ip;
--INPUT
	NEXTIP_REGSTER :
	process(I_CLK,I_RST,I_WRIP,I_WRPLUS,I_DATA,ip,I_PLUSOP,I_PLUSMOD)
	begin
		if (I_RST = RST_ACT) then
			ip <= "0000000000000000";
		elsif(I_CLK'event and I_CLK='0')then
			--WRITE to IP
			if    (I_WRIP = '1' and I_WRPlUS = '0') then
				ip <= I_DATA;
			--write NEXT OPcode IP
			elsif (I_WRIP = '0' and I_WRPLUS = '1') then
				ip <= ip + (("0000000000000"&I_PLUSOP) + ("00000000000000"&I_PLUSMOD)); --write nextIP
			end if;
		end if;
	end process;

end RTL;