bcu.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library synplify;
use synplify.attributes.all;
  
entity BCU is
	port( I_CLK        :  in std_logic;
          I_RST        :  in std_logic;	
          I_RDY        :  in std_logic;	  
          I_RD         :  in std_logic;
          I_BW         :  in std_logic;
          I_WR         :  in std_logic;
          I_ADROUT     :  in std_logic;
          I_IO         :  in std_logic;
          I_EUCRST     :  in std_logic;
          I_FE         :  in std_logic;
          I_IPF        :  in std_logic;
          I_IRF        :  in std_logic;
          I_OADR       :  in std_logic_vector(15 downto 0 );
          I_PADR       :  in std_logic_vector(19 downto 0 );
          I_DATA2MEM   :  in std_logic_vector(15 downto 0 );
          I_EXTBUS     :  in std_logic_vector(15 downto 0 );
          O_ENDRC      : out std_logic;
          O_ENDWC      : out std_logic;
          O_IO         : out std_logic;
          O_ODD        : out std_logic;
          O_QUEF       : out std_logic;
          O_BHE        : out std_logic;
          O_DATA2EU    : out std_logic_vector(15 downto 0 );
          O_DATA2QUE   : out std_logic_vector(15 downto 0 );
          O_DEN_N      : out std_logic;
          O_DTR        : out std_logic;
          O_RD_N       : out std_logic;
		  O_ALE        : out std_logic;
          O_WR_N       : out std_logic;
          O_BCUSTATE_V : out std_logic_vector( 2 downto 0 );
		  O_DCSTATE_V  : out std_logic_vector( 3 downto 0 );
          O_A19A16     : out std_logic_vector( 3 downto 0 );
          O_EXTBUS     : out std_logic_vector(15 downto 0 )
		  ); 
end BCU;
  
architecture RTL of BCU is
 
signal BCU_BCF     : std_logic;
signal BCU_DATA2EU : std_logic_vector(15 downto 0 );
signal DC_ADR      : std_logic_vector(19 downto 0 );
signal DC_DATA2MEM : std_logic_vector(15 downto 0 );
signal DC_FE       : std_logic;
signal DC_RD       : std_logic;
signal DC_WR       : std_logic;

component MBCU
	port( I_CLK		   :  in std_logic;
		  I_RST        :  in std_logic;
		  I_RDY        :  in std_logic; --if '0', BUS cycle become idle state.
		  I_EUCRST     :  in std_logic; --from EUC reset signal
	      I_DATA2MEM   :  in std_logic_vector(15 downto 0); --data in from DC
          I_PADR       :  in std_logic_vector(19 downto 0); --address in form DC
          I_RD         :  in std_logic; --signal read from memory
          I_WR         :  in std_logic; --signal write to memory 
          I_FE         :  in std_logic; --signal fetch from DC
		  I_EXTBUS     :  in std_logic_vector(15 downto 0); --external address/data 16bit bus
		  O_DATA2EU    : out std_logic_vector(15 downto 0); --data out to DC
          O_A19A16     : out std_logic_vector( 3 downto 0); --output adress 19~16bit
		  O_EXTBUS     : out std_logic_vector(15 downto 0); --external address/data 16bit bus
		  O_RD_N       : out std_logic; --when read from I/O device = 'L'
          O_WR_N       : out std_logic; --when write to I/O device = 'L'
          O_DEN_N      : out std_logic; --if there are effective data on the AD_BUS ='L'
		  O_ALE        : out std_logic; --if output adress = 'H'
          O_DTR        : out std_logic; --if data out to RAM = 'H' 
		  O_ENDBC      : out std_logic; --end 1 bus cycle = '1' 
		  O_BCUSTATE_V : out std_logic_vector( 2 downto 0) --current state(test)
		  ); 
end component;

component DCBCU
	generic( PADRW : integer;
	         OADRW : integer;
	         DATAW : integer;
			 BYTEW : integer
			 );
    port( I_CLK		  :  in std_logic;
		  I_RST       :  in std_logic;
		  I_EUCRST    :  in std_logic;                      --from EUC reset signal
	      I_RD        :  in std_logic;                      --read signal from EU
          I_WR        :  in std_logic;                      --write signal from EU
		  I_BW        :  in std_logic;                      --byte = '0', word = '1'
		  I_FE        :  in std_logic;                      --fetch signal from QUE
		  I_IPF       :  in std_logic;                      --address out flag from AD_ADD(FETCH)
		  I_IRF       :  in std_logic;                      --address out flag from AD_ADD
		  I_IO        :  in std_logic;                      --I/O device access => '1'(READ,WRITE)
		  I_ADROUT    :  in std_logic;
		  I_ENDBC     :  in std_logic;                      --end 1 bus cycle = '1' 
          I_DATA2EU   :  in std_logic_vector(DATAW-1 downto 0);  --data from BCU
		  I_OADR      :  in std_logic_vector(OADRW-1 downto 0);  --immediate address from EUC_CU 
		  I_DATA2MEM  :  in std_logic_vector(DATAW-1 downto 0);  --data from EU
          I_PADR      :  in std_logic_vector(PADRW-1 downto 0);  --address in from add 
          O_RD        : out std_logic;                     --read signal to BCU
          O_WR        : out std_logic;                     --write signal to BCU
		  O_FE        : out std_logic;                     --fetch signal to BCU
          O_ENDRC     : out std_logic;                     --if data out to EU,'1'
		  O_ENDWC     : out std_logic;                     --end write mem => '1'
          O_BHE       : out std_logic;                     --memory access control signal(&A0)
		  O_ODD       : out std_logic;                     --I_ADR(0)='1'(odd) => '1'
		  O_QUEF      : out std_logic;                     --out QUE_IN = '1'
		  O_IO        : out std_logic;                     --memory access => '0' I/O device => '1'
		  O_DCSTATE_V : out std_logic_vector( 3 downto 0);
          O_DATA2EU   : out std_logic_vector(DATAW-1 downto 0); --data out to EU
		  O_DATA2MEM  : out std_logic_vector(DATAW-1 downto 0); --data out to BCU
		  O_DATA2QUE  : out std_logic_vector(DATAW-1 downto 0); --OP code to QUE
          O_PADR      : out std_logic_vector(PADRW-1 downto 0)  --address out to BCU
		  );                     --address from ECU to BCU  
end component;

begin 
	MBCU_BCU : MBCU
    port map( 
		I_CLK => I_CLK,
		I_RST => I_RST,
		I_RDY => I_RDY,
		I_EUCRST => I_EUCRST,
	    I_DATA2MEM => DC_DATA2MEM,
        I_PADR => DC_ADR,
        I_RD => DC_RD,
        I_WR => DC_WR,
        I_FE => DC_FE,
		I_EXTBUS => I_EXTBUS,
		O_DATA2EU => BCU_DATA2EU,
        O_A19A16 => O_A19A16,
		O_EXTBUS => O_EXTBUS,
		O_RD_N => O_RD_N,
        O_WR_N => O_WR_N,
        O_DEN_N => O_DEN_N,
		O_ALE => O_ALE,
        O_DTR => O_DTR,
		O_ENDBC => BCU_BCF,
		O_BCUSTATE_V => O_BCUSTATE_V
		); 

	DCBCU_BCU : DCBCU
	generic map( 
		PADRW =>20,
	    OADRW =>16,
	    DATAW =>16,
		BYTEW =>8
		)
    port map( 
		I_CLK => I_CLK,
		I_RST => I_RST,
	    I_RD => I_RD,
        I_WR => I_WR,
		I_BW => I_BW,
		I_FE => I_FE,
		I_IPF => I_IPF,
		I_IRF => I_IRF,
		I_ENDBC => BCU_BCF,
        I_PADR => I_PADR,
        I_DATA2EU => BCU_DATA2EU,
		I_OADR => I_OADR,
		I_EUCRST => I_EUCRST,
		I_ADROUT => I_ADROUT,
		I_DATA2MEM => I_DATA2MEM,
		I_IO => I_IO,
        O_DATA2EU => O_DATA2EU,
		O_DATA2MEM => DC_DATA2MEM,
		O_DATA2QUE => O_DATA2QUE,
        O_ENDRC => O_ENDRC,
		O_ENDWC => O_ENDWC,
        O_PADR => DC_ADR,
		O_DCSTATE_V => O_DCSTATE_V,
        O_BHE => O_BHE,
		O_ODD => O_ODD,
		O_QUEF => O_QUEF,
		O_FE => DC_FE,
        O_RD => DC_RD,
        O_WR => DC_WR,
		O_IO => O_IO
		);   

end RTL;