fifo.vhd

X8086的VHDL源码

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--   FILE NAME : fifo_FETCH.vhd
--   FUNCTION  : FIFO
--   AUTHOR    : Kazuma Mishima
--   DATE      : 5/2001
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use WORK.UPAC.all;

entity FIFO is
	generic( WORD : integer ;
    	     K    : integer );             
    port( I_CLK      :  in std_logic;
		  I_RST      :  in std_logic;
		  I_QUERST   :  in std_logic; --Que reset signal
	      I_QUEWR_N  :  in std_logic; --write signal (furonri)
	      I_RDQUE    :  in std_logic; --read signal
		  I_CQUEF    :  in std_logic; --write QUE => '1'
    	  I_BDATA    :  in std_logic_vector(K-1 downto 0); --input instruction code
          O_BDATA    : out std_logic_vector(K-1 downto 0); --output instruction code
          O_FE       : out std_logic; --fetch signal
		  O_CQUEF    : out std_logic; --end write QUE => '1'
		  O_QUEFULL  : out std_logic; --full flag
          O_QUEEMPTY : out std_logic  --empty flag
		  ); 
end FIFO;

architecture RTL of FIFO is

--the difinition of QUE
type   QUE_DATA is array (0 to WORD-1) of std_logic_vector(K-1 downto 0);
signal que      : QUE_DATA;
signal wp       : integer range 0 to WORD-1;
signal rp       : integer range 0 to WORD-1;  --read pointer & write pointer
signal in_full  : std_logic;
signal in_empty : std_logic;     --full & empty (internal signal)
signal wrque    : std_logic;

begin      
	O_QUEFUll  <= in_full;
	O_QUEEMPTY <= in_empty;
	O_BDATA    <= que(rp);
	O_CQUEF    <= wrque;

--write to the QUE
	WRITE_TO_THE_QUE : 
	process(I_CLK,I_QUEWR_N,in_full,I_BDATA)
	begin
		if(I_CLK'event and I_CLK = '0')then
			if(I_QUEWR_N = '0' and in_full='0')then
				que(wp) <= I_BDATA;
			end if;
		end if;
	end process;
--WP
	WritePointer : 
	process(I_CLK,I_RST,I_QUERST,I_QUEWR_N,in_full,wp)
	begin
		if (I_RST = RST_ACT)then
			wp <= 0;
		elsif (I_CLK'event and I_CLK ='0')then
			if (I_QUERST='1')then
				wp <= 0;
			else
				if (I_QUEWR_N='0' and in_full ='0')then
					if (wp = WORD-1)then
						wp <= 0;
					else
						wp <= WP+1;
					end if;
				end if;
			end if;
		end if;
	end process;
--RP
    ReadPointer : 
	process(I_CLK,I_RST,I_QUERST,I_RDQUE,in_empty,rp)
	begin
		if (I_RST = RST_ACT)then
				rp <= WORD-1;
		elsif (I_CLK'event and I_CLK ='0')then
			if (I_QUERST='1')then
				rp <= WORD-1;
			else
				if (I_RDQUE='1' and in_empty='0')then
					if (rp = WORD-1)then
						rp <= 0;
					else
						rp <= rp+1;
					end if;
				end if;
			end if;
		end if;
	end process;
--Flag IN_EMPTY

	EMPTY_FRAG : 
	process(I_CLK,I_RST,I_QUERST,rp,wp,I_RDQUE,I_QUEWR_N,in_empty)
	begin
		if (I_RST = RST_ACT)then 
			in_empty <= '1';
		elsif (I_CLK'event and I_CLK='0')then
			if (I_QUERST='1')then
				in_empty <= '1';
			else
				if ((rp = wp-2 or (rp = WORD-1 and wp = 1) or (rp = WORD-2 and wp=0)) 
				and I_RDQUE='1' and I_QUEWR_N='1')then
					in_empty <= '1';
				elsif (in_empty='1' and I_QUEWR_N='0')then
					in_empty <= '0';
				end if;				
			end if;
		end if;
	end process;
--Flag IN_FULL
    FULL_FRAG : 
	process(I_CLK,I_RST,I_QUERST,rp,wp,I_QUEWR_N,I_RDQUE,in_full)
	begin
		if (I_RST = RST_ACT)then
			in_full <= '0';
		elsif (I_CLK'event and I_CLK='0')then
			if (I_QUERST='1')then
				in_full <= '0';
			else
				if (rp = wp and I_QUEWR_N='0' and I_RDQUE='0')then
					in_full <= '1';
				elsif (in_full = '1' and I_RDQUE = '1')then
					in_full <= '0';
				end if;
			end if;
		end if;
	end process;
--fetch singal
	FETCH_SIGNAL : 
	process(I_CLK,I_RST,I_QUERST,in_full,rp,wp)
	begin
		if (I_RST = RST_ACT)then
			O_FE <= '1';
		elsif (I_CLK'event and I_CLK='0')then
			if (I_QUERST='1')then
				O_FE <= '1';
			else
				if (in_full = '1' or rp = wp) then --full or full-1
					O_FE <= '0';
				else
					O_FE <= '1';
				end if;
  			end if;
		end if;
	end process;
--end write que flag
	END_WRITE : 
	process(I_CLK,I_RST,I_CQUEF) 
	begin
		if(I_RST = RST_ACT ) then
			wrque <= '0';
		elsif (I_CLK'event and I_CLK='0') then
			wrque <= I_CQUEF;
		end if;
	end process;

end RTL;