freg.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.UPAC.ALL;

entity FREG is
    port( I_CLK  :  in std_logic;
          I_RST  :  in std_logic;
		  I_FREG :  in std_logic_vector( 8 downto 0);
		  I_FREN :  in std_logic_vector(17 downto 0);
		  O_CFR  : out std_logic;
		  O_AFR  : out std_logic;
          O_FREG : out std_logic_vector( 8 downto 0)
		  );
end FREG;

architecture RTL of FREG is

signal o_fr :std_logic;
signal d_fr :std_logic;
signal i_fr :std_logic;
signal t_fr :std_logic;
signal s_fr :std_logic;
signal z_fr :std_logic;
signal a_fr :std_logic;
signal p_fr :std_logic;
signal c_fr :std_logic;

begin
	O_FREG <= o_fr&d_fr&i_fr&t_fr&s_fr&z_fr&a_fr&p_fr&c_fr; 
	O_CFR  <= c_fr;
    O_AFR  <= a_fr;

	Overflow_Frag : 
	process(I_CLK,I_RST,I_FREN(17 downto 16),I_FREG(OFR))
	begin
		if (I_RST ='0')then
			o_fr <= '0';
		elsif (I_CLK'event and I_CLK = '0')then
			if    (I_FREN(17 downto 16)="00")then--STORE
				o_fr <= I_FREG(OFR);
			elsif (I_FREN(17 downto 16)="10")then--RESET
				o_fr <= '0';
			elsif (I_FREN(17 downto 16)="11")then--SET
				o_fr <= '1';
			end if;--IF "01"THEN LATCH
		end if;
	end process;

	Direction_Frag : 
	process(I_CLK,I_RST,I_FREN(15 downto 14),I_FREG(DFR))
	begin
		if (I_RST ='0')then
			d_fr <= '0';
		elsif (I_CLK'event and I_CLK = '0')then
			if    (I_FREN(15 downto 14)="00")then--STORE
				d_fr <= I_FREG(DFR);
			elsif (I_FREN(15 downto 14)="10")then--RESET
				d_fr <= '0';
			elsif (I_FREN(15 downto 14)="11")then--SET
				d_fr <= '1';
			end if;--IF "01"THEN LATCH
		end if;
	end process;

	Interrupt_enable_Frag :
	process(I_CLK,I_RST,I_FREN(13 downto 12),I_FREG(IFR))
	begin
		if (I_RST ='0')then
			i_fr <= '0';
		elsif (I_CLK'event and I_CLK = '0')then
			if    (I_FREN(13 downto 12)="00")then--STORE
				i_fr <= I_FREG(IFR);
			elsif (I_FREN(13 downto 12)="10")then--RESET
				i_fr <= '0';
			elsif (I_FREN(13 downto 12)="11")then--SET
				i_fr <= '1';
			end if;--IF "01"THEN LATCH
		end if;
	end process;

	Trap_Frag : 
	process(I_CLK,I_RST,I_FREN(11 downto 10),I_FREG(TFR))
	begin
		if (I_RST ='0')then
			t_fr <= '0';
		elsif (I_CLK'event and I_CLK = '0')then
			if    (I_FREN(11 downto 10)="00")then--STORE
				t_fr <= I_FREG(TFR);
			elsif (I_FREN(11 downto 10)="10")then--RESET
				t_fr <= '0';
			elsif (I_FREN(11 downto 10)="11")then--SET
				t_fr <= '1';
			end if;--IF "01"THEN LATCH
		end if;
	end process;

	Sign_Frag :
	process(I_CLK,I_RST,I_FREN(9 downto 8),I_FREG(SFR))
	begin
		if (I_RST ='0')then
			s_fr <= '0';
		elsif (I_CLK'event and I_CLK = '0')then
			if    (I_FREN( 9 downto  8)="00")then--STORE
				s_fr <= I_FREG(SFR);
			elsif (I_FREN( 9 downto  8)="10")then--RESET
				s_fr <= '0';
			elsif (I_FREN( 9 downto  8)="11")then--SET
				s_fr <= '1';
			end if;--IF "01"THEN LATCH
		end if;
	end process;

	Zero_Frag :
	process(I_CLK,I_RST,I_FREN(7 downto 6),I_FREG(ZFR))
	begin
		if (I_RST ='0')then
			z_fr <= '0';
		elsif (I_CLK'event and I_CLK = '0')then
			if    (I_FREN( 7 downto  6)="00")then--STORE
				z_fr <= I_FREG(ZFR);
			elsif (I_FREN( 7 downto  6)="10")then--RESET
				z_fr <= '0';
			elsif (I_FREN( 7 downto  6)="11")then--SET
				z_fr <= '1';
			end if;--IF "01"THEN LATCH
		end if;
	end process;

	Auxiliary_carry_Frag:
	process(I_CLK,I_RST,I_FREN(5 downto 4),I_FREG(AFR))
	begin
		if (I_RST ='0')then
			a_fr <= '0';
		elsif (I_CLK'event and I_CLK = '0')then
			if    (I_FREN( 5 downto  4)="00")then--STORE
				a_fr <= I_FREG(AFR);
			elsif (I_FREN( 5 downto  4)="10")then--RESET
				a_fr <= '0';
			elsif (I_FREN( 5 downto  4)="11")then--SET
				a_fr <= '1';
			end if;--IF "01"THEN LATCH
		end if;
	end process;

	Parity_Frag :
	process(I_CLK,I_RST,I_FREN(3 downto 2),I_FREG(PFR))
	begin
		if (I_RST ='0')then
			p_fr <= '0';
		elsif (I_CLK'event and I_CLK = '0')then
			if    (I_FREN( 3 downto  2)="00")then--STORE
				p_fr <= I_FREG(PFR);
			elsif (I_FREN( 3 downto  2)="10")then--RESET
				p_fr <= '0';
			elsif (I_FREN( 3 downto  2)="11")then--SET
				p_fr <= '1';
			end if;--IF "01"THEN LATCH
		end if;
	end process;

	Carry_Frag :
	process(I_CLK,I_RST,I_FREN(1 downto 0),I_FREG(CFR))
	begin
		if (I_RST ='0')then
			c_fr <= '0';
		elsif (I_CLK'event and I_CLK = '0')then
			if    (I_FREN( 1 downto  0)="00")then--STORE
				c_fr <= I_FREG(CFR);
			elsif (I_FREN( 1 downto  0)="10")then--RESET
				c_fr <= '0';
			elsif (I_FREN( 1 downto  0)="11")then--SET
				c_fr <= '1';
			end if;--IF "01"THEN LATCH
		end if;
	end process;

end RTL;