mp8086.fit.rpt

X8086的VHDL源码

Fitter report for MP8086
Fri Jan 12 16:12:47 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Input Pins
  6. Output Pins
  7. All Package Pins
  8. Control Signals
  9. Global & Other Fast Signals
 10. Carry Chains
 11. Cascade Chains
 12. Embedded Cells
 13. Non-Global High Fan-Out Signals
 14. Local Routing Interconnect
 15. MegaLAB Interconnect
 16. LAB External Interconnect
 17. MegaLAB Usage Summary
 18. Row Interconnect
 19. LAB Column Interconnect
 20. ESB Column Interconnect
 21. Fitter Resource Usage Summary
 22. Fitter Resource Utilization by Entity
 23. Delay Chain Summary
 24. I/O Bank Usage
 25. Fitter RAM Summary
 26. Pin-Out File
 27. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Fri Jan 12 16:12:47 2007    ;
; Quartus II Version    ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name         ; MP8086                                   ;
; Top-level Entity Name ; MP8086                                   ;
; Family                ; APEX20KE                                 ;
; Device                ; EP20K400EBC652-3                         ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 5,721 / 16,640 ( 34 % )                  ;
; Total pins            ; 426 / 488 ( 87 % )                       ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 4,096 / 212,992 ( 2 % )                  ;
; Total PLLs            ; 0                                        ;
+-----------------------+------------------------------------------+