mpx2in1outb.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MPX2IN1OUTB is
    port( I_SW :  in std_logic;
		  I_DATA01  :  in std_logic_vector( 5 downto 0);      
		  I_DATA11  :  in std_logic_vector( 8 downto 0);
          O_DATA    : out std_logic_vector( 8 downto 0)
		  );
end MPX2IN1OUTB;

architecture RTL of MPX2IN1OUTB is

begin
	process (I_SW,I_DATA01,I_DATA11) 
	begin
		if (I_SW = '0') then
			O_DATA <= I_DATA01(5)&"000"&I_DATA01(4 downto 0);
		else
			O_DATA <= I_DATA11;
		end if;
	end process;
end RTL;