cueu.vhd

X8086的VHDL源码

		  O_NFE        : out std_logic; --OEUC not fetch signal
		  O_SE         : out std_logic; --sign extension('1'extension,'0'null)
		  O_D16HL      : out std_logic;	-- when 16bit(8bit&8bit)data store to TRU('1'=>high)
		  O_AAM        : out std_logic;	--set mode(div for AAM)
		  O_MULCS      : out std_logic_vector( 1 downto 0); --tmp control 
		  O_OP_V       : out std_logic_vector( 7 downto 0);
		  O_EUCSTATE_V : out std_logic_vector( 8 downto 0) --EUC STATE (for symulation)			  
		  ); 
end component;
component DIVCU
	port( I_CLK      :  in std_logic;
          I_RST      :  in std_logic;    
          I_DIV      :  in std_logic;
          I_IDIV     :  in std_logic;
          I_QUOF     :  in std_logic;
          I_AAM      :  in std_logic;
          I_BW       :  in std_logic;
          I_MOD      :  in std_logic_vector( 1 downto 0 );
          I_RM       :  in std_logic_vector( 2 downto 0 );
          I_BSIGNDIV :  in std_logic;
          I_SIGNDIV  :  in std_logic;
          I_SIGNPLS  :  in std_logic;
          I_SIGNTR2  :  in std_logic;
          O_TMPCS    : out std_logic_vector( 4 downto 0 );
          O_BUSCS    : out std_logic_vector( 4 downto 0 );
          O_GRSEL    : out std_logic_vector( 3 downto 0 );
          O_GRRW     : out std_logic;
          O_QUOF     : out std_logic;
          O_DIVF     : out std_logic;
          O_ENDDIV   : out std_logic;
          O_DIVSTATE : out std_logic_vector( 3 downto 0 );
          O_TYPEZERO : out std_logic
		  );
end component;

component MPX8IN4OUTA	
	generic( S1W : integer :=  4; --memory WORD
			 S2W : integer :=  5;
			 S3W : integer :=  4
			 ); 
    port( I_SW       :  in std_logic;
          I_DATA12   :  in std_logic_vector( S2W-1 downto 0 ); --I_SW=1
          I_DATA13   :  in std_logic_vector( S3W-1 downto 0 ); --I_SW=1
          I_DATA14   :  in std_logic;                          --I_SW=1
          I_DATA01   :  in std_logic_vector( S1W-1 downto 0 ); --I_SW=0
          I_DATA02   :  in std_logic_vector( S2W-1 downto 0 ); --I_SW=0
          I_DATA03   :  in std_logic_vector( S3W-1 downto 0 ); --I_SW=0
          I_DATA04   :  in std_logic;                          --I_SW=0
          O_DATA1    : out std_logic_vector( S1W-1 downto 0 );
          O_DATA2    : out std_logic_vector( S2W-1 downto 0 );
          O_DATA3    : out std_logic_vector( S3W-1 downto 0 );
          O_DATA4    : out std_logic
		  );
end component;
 
begin
 
	T_CU_CUEU : CU
	port map( 
		I_CLK => I_CLK,
        I_RST => I_RST,
        I_MOD => EUC_MOD,
        I_RM => EUC_RM,
		I_BW => EUC_BW,
        I_EA => EUC_EA,
        I_RDQUE => EUC_RDQUE,
        I_D16HL => EUC_D16HL,
        I_SE => EUC_SE,
        I_TMPRW => EUC_TMPRW,
        I_BUSCS => DIVMPX_BUSCS,
        I_GRSEL => DIVMPX_GRSEL,
        I_QUEEMPTY => I_QUEEMPTY,
        I_BDATA => I_BDATA,
        I_BIUDATA => I_BIUDATA,
        O_D16HL => CSSEL_D16HL,
        O_RDQUE => O_RDQUE,
        O_SE => CSSEL_SE,
        O_BUSCS => CSSEL_BUSCS,
        O_GRSEL => CSSEL_GRSEL,
        O_TMPRW => CSSEL_TMPRW,
        O_BIUDATA => ULINK_BIUDATA,
        O_EARQ => STDEC_EARQ,
        O_EACUSTATE_V => O_EACUSTATE
		); 
 
	T_EU_CUEU : EU
	port map ( 
        I_CLK => I_CLK,
		I_RST => I_RST,
        I_S77 => I_S77,
        I_ALUCS => DIVMPX_ALUCS,   
        I_BW => EUC_BW,
        I_BIUDATA => ULINK_BIUDATA,
        I_BUSCS => CSSEL_BUSCS,
        I_D16HL => CSSEL_D16HL,
        I_FRSEL => EUC_FRSEL,
        I_DIVF => DIVDEC_DIVF,
        I_EA => EUC_EA,
        I_FREN => EUC_FREGEF,
        I_GRRW => DIVMPX_GRRW,
        I_GRSEL => CSSEL_GRSEL,
        I_MULHL => EUC_MULHL,
        I_QUOF => DIVDEC_QUOF,
        I_TMPRW => CSSEL_TMPRW,
        I_TMPCS => DIVDEC_TMPCS,
        I_1SETTR2 => EUC_1SET,
        I_ADJUST => EUC_ADJUST,
        I_MULCS => EUC_MULCS,
        I_REG3 => EUC_REG3,
        I_SE => CSSEL_SE,
        I_2SETTR2 => EUC_TMP2,
        I_USECARRY => EUC_UC,
        O_QUOF => ALU_QUOF,
        O_EUDATA => EUINBUS_DATA2BIU,
        O_FREG => FR_FREG,
        O_BSIGNDIV => TRU_BMSBDIVREG,
        O_BSIGNTR1 => TRU_BMSBTREG1,
        O_LSBTR2 => TRU_LSBTREG2,
        O_SIGNDIV => TRU_MSBDIVREG,
        O_SIGNPLS => TRU_MSBPLUSREG,
        O_SIGNTR1 => TRU_MSBTREG1,
        O_SIGNTR2 => TRU_MSBTREG2,
	    O_ALUDATA_V => O_ALUDATA_V,
        O_REG1 => TRU_TREG1_V,
        O_REG2 => O_REG2,
        O_AX_V => O_AX_V,
        O_BP_V => O_BP_V,
        O_BX_V => O_BX_V,
        O_CX_V => GRU_CX_V,
        O_DI_V => O_DI_V,
        O_DX_V => O_DX_V,
        O_SI_V => O_SI_V,
        O_SP_V => O_SP_V
        );

	EUC_CUEU : EUC
    port map ( 
		I_CLK => I_CLK,
        I_RST => I_RST,
		I_BDATA => I_BDATA,
	   	I_QUEEMPTY => I_QUEEMPTY,
		I_EARQ => STDEC_EARQ,
		I_ENDRC => I_ENDRC,
		I_ENDWC => I_ENDWC,
		I_ENDDIV => DIVDEC_ENDDIV,
		I_FREG => FR_FREG,
		I_DATA => EUINBUS_DATA2BIU,
		I_CX => GRU_CX_V,
        I_NEXTIP => I_NEXTIP,
		I_SIGNTR1 => TRU_MSBTREG1,
		I_BSIGNTR1 => TRU_BMSBTREG1,
		I_REG1 => TRU_TREG1_V,
		I_LSBTR2 => TRU_LSBTREG2,
		O_RD => O_RD,    
	 	O_WR => O_WR,
		O_RDQUE => EUC_RDQUE,
        O_BUSCS => EUC_BUSCS,
        O_EA => EUC_EA,
		O_BW => EUC_BW,
        O_GRSEL => EUC_GRSEL,
		O_MOD => EUC_MOD,
        O_RM => EUC_RM,
        O_TMPRW => EUC_TMPRW,
        O_ALUCS => EUC_ALUCS,    
        O_FRSEL => EUC_FRSEL,
        O_FREN => EUC_FREGEF,
        O_GRRW => EUC_GRRW,
        O_MULHL => EUC_MULHL,
		O_CSR => O_CSR,
		O_SRSEL => O_SRSEL,
		O_WRIP => O_WRIP,
		O_WRIR => O_WRIR,
		O_WRSR => O_WRSR,
		O_1SETTR2 => EUC_1SET,
		O_2SETTR2 => EUC_TMP2,  
		O_RDSR => O_RDSR,
		O_IO => O_IO,
		O_OADR => O_OADR,
		O_RDIR => O_RDIR,
		O_DIV => EUC_DIV,
		O_IDIV => EUC_IDIV,
		O_EAPLUS2 => O_EAPLUS2,
		O_MDTF => O_MDTF,
		O_REG3 => EUC_REG3,
		O_DATA => O_EUCDATA,
		O_2EU => O_2EU,
        O_2BIU => O_2BIU,
		O_2SR => O_2SR,
		O_USECARRY => EUC_UC,
		O_ADJUST => EUC_ADJUST,
		O_HLT => O_HLT,
		O_WRPLUS => O_WRPLUS,
        O_PLUSOP => O_PLUSOP,
		O_PLUSMOD => O_PLUSMOD,
		O_QUERST => O_QUERST,
		O_EUCRST => O_EUCRST,
		O_ADROUT => O_ADROUT,
		O_NFE => O_NFE,
		O_ORPCSR => O_ORPCSR,
		O_ORPSRSEL => O_ORPSRSEL,   
		O_SE => EUC_SE,
		O_D16HL => EUC_D16HL,   
		O_AAM => EUC_AAM,
		O_MULCS => EUC_MULCS,
		O_OP_V => O_OP_V,
		O_EUCSTATE_V => O_EUCSTATE_V 
		); 

	T_DIVCU_CUEU : DIVCU
	port map( 
		I_CLK => I_CLK,
        I_RST => I_RST,
        I_DIV => EUC_DIV,
        I_IDIV => EUC_IDIV,
        I_QUOF => ALU_QUOF,
        I_AAM => EUC_AAM,
        I_BW => EUC_BW,
        I_MOD => EUC_MOD,
        I_RM => EUC_RM,
        I_BSIGNDIV => TRU_BMSBDIVREG,
        I_SIGNDIV => TRU_MSBDIVREG,
        I_SIGNPLS => TRU_MSBPLUSREG,
        I_SIGNTR2 => TRU_MSBTREG2,
        O_TMPCS => DIVDEC_TMPCS,
        O_BUSCS => DIVDEC_BUSCS,
        O_GRSEL => DIVDEC_GRSEL,
        O_GRRW => DIVDEC_GRRW,
        O_QUOF => DIVDEC_QUOF,
        O_DIVF => DIVDEC_DIVF,
        O_ENDDIV => DIVDEC_ENDDIV,
        O_DIVSTATE => O_DIVSTATE,
        O_TYPEZERO => O_TYPEZERO
		);

	MPX8IN4OUTA_CUEU : MPX8IN4OUTA
	generic map( 
		S1W => 4, 
		S2W => 5,
		S3W => 4
		)
    port map ( 
		I_SW => EUC_DIV,
        I_DATA12 => DIVDEC_BUSCS,
        I_DATA13 => DIVDEC_GRSEL,
        I_DATA14 => DIVDEC_GRRW,
        I_DATA01 => EUC_ALUCS,
        I_DATA02 => EUC_BUSCS,
        I_DATA03 => EUC_GRSEL,
        I_DATA04 => EUC_GRRW,
        O_DATA1 => DIVMPX_ALUCS,
        O_DATA2 => DIVMPX_BUSCS,
        O_DATA3 => DIVMPX_GRSEL,
        O_DATA4 => DIVMPX_GRRW
		);

	O_CX_V    <= GRU_CX_V;  
    O_BW      <= EUC_BW;  
    O_MOD     <= EUC_MOD;    
	O_RM      <= EUC_RM;     
	O_EARQ    <= STDEC_EARQ;     
	O_EUDATA <= EUINBUS_DATA2BIU;
	O_FREG    <= FR_FREG;
	O_REG1    <= TRU_TREG1_V;    

end RTL;