cueu.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library synplify;
use synplify.attributes.all;
  
entity CUEU is
	port( I_CLK        :  in std_logic;
          I_RST        :  in std_logic;
          I_S77        :  in std_logic;
          I_QUEEMPTY   :  in std_logic;
          I_ENDRC      :  in std_logic;
          I_ENDWC      :  in std_logic;
          I_BDATA      :  in std_logic_vector( 7 downto 0 );
          I_BIUDATA    :  in std_logic_vector(15 downto 0 );
          I_NEXTIP     :  in std_logic_vector(15 downto 0 );
          O_EUCRST     : out std_logic;
          O_QUERST     : out std_logic;
          O_BW         : out std_logic;
          O_MOD        : out std_logic_vector( 1 downto 0 );
          O_RM         : out std_logic_vector( 2 downto 0 );
          O_RDSR       : out std_logic;
          O_WRSR       : out std_logic;
          O_WRIP       : out std_logic;
          O_RDIR       : out std_logic;
          O_WRIR       : out std_logic;
          O_RD         : out std_logic;
          O_WR         : out std_logic;
          O_ADROUT     : out std_logic;
          O_IO         : out std_logic;
          O_MDTF       : out std_logic;
          O_NFE        : out std_logic;
          O_WRPLUS     : out std_logic;
          O_EAPLUS2    : out std_logic;
          O_2BIU       : out std_logic;
          O_2EU        : out std_logic;
          O_2SR        : out std_logic;
          O_HLT        : out std_logic;
          O_CSR        : out std_logic;
          O_SRSEL      : out std_logic_vector( 1 downto 0 );
          O_ORPCSR     : out std_logic;
          O_ORPSRSEL   : out std_logic_vector( 1 downto 0 );
          O_RDQUE      : out std_logic;
          O_EARQ       : out std_logic;
          O_TYPEZERO   : out std_logic;
          O_PLUSMOD    : out std_logic_vector( 1 downto 0 );
          O_PLUSOP     : out std_logic_vector( 2 downto 0 );
          O_EUDATA     : out std_logic_vector(15 downto 0 );
          O_EUCDATA    : out std_logic_vector(15 downto 0 );
          O_OADR       : out std_logic_vector(15 downto 0 );
		  O_OP_V       : out std_logic_vector( 7 downto 0 );
          O_EUCSTATE_V : out std_logic_vector( 8 downto 0 );
          O_DIVSTATE   : out std_logic_vector( 3 downto 0 );
          O_EACUSTATE  : out std_logic_vector( 2 downto 0 );
          O_FREG       : out std_logic_vector( 8 downto 0 );
		  O_ALUDATA_V  : out std_logic_vector(15 downto 0 );
          O_REG1       : out std_logic_vector(15 downto 0 );
          O_REG2       : out std_logic_vector(15 downto 0 );
          O_AX_V       : out std_logic_vector(15 downto 0 );
          O_BP_V       : out std_logic_vector(15 downto 0 );
          O_BX_V       : out std_logic_vector(15 downto 0 );
          O_CX_V       : out std_logic_vector(15 downto 0 );
          O_DI_V       : out std_logic_vector(15 downto 0 );
          O_DX_V       : out std_logic_vector(15 downto 0 );
          O_SI_V       : out std_logic_vector(15 downto 0 );
          O_SP_V       : out std_logic_vector(15 downto 0 )        
		  ); 
end CUEU;
  
architecture RTL of CUEU is
 
signal GRU_CX_V         : std_logic_vector(15 downto 0);--
signal EUC_BW           : std_logic;                    --
signal EUC_MOD          : std_logic_vector( 1 downto 0);--
signal EUC_RM           : std_logic_vector( 2 downto 0);--
signal STDEC_EARQ       : std_logic;                    --
signal EUINBUS_DATA2BIU : std_logic_vector(15 downto 0);--
signal FR_FREG          : std_logic_vector( 8 downto 0);--
signal TRU_TREG1_V      : std_logic_vector(15 downto 0);--
signal ALU_QUOF         : std_logic;
signal CSSEL_D16HL      : std_logic;
signal CSSEL_SE         : std_logic;
signal CSSEL_BUSCS      : std_logic_vector( 4 downto 0);
signal CSSEL_GRSEL      : std_logic_vector( 3 downto 0);
signal CSSEL_TMPRW      : std_logic_vector( 1 downto 0);
signal ULINK_BIUDATA    : std_logic_vector(15 downto 0);
signal DIVDEC_ENDDIV    : std_logic;
signal DIVDEC_BUSCS     : std_logic_vector( 4 downto 0 );
signal DIVDEC_DIVF      : std_logic;
signal DIVDEC_GRRW      : std_logic;
signal DIVDEC_GRSEL     : std_logic_vector( 3 downto 0 );
signal DIVDEC_QUOF      : std_logic;
signal DIVDEC_TMPCS     : std_logic_vector( 4 downto 0 );
signal EUC_EA           : std_logic;
signal EUC_1SET         : std_logic;
signal EUC_AAM          : std_logic;
signal EUC_ADJUST       : std_logic_vector( 1 downto 0 );
signal EUC_ALUCS        : std_logic_vector( 3 downto 0 );
signal EUC_BUSCS        : std_logic_vector( 4 downto 0 );
signal EUC_D16HL        : std_logic;
signal EUC_FRSEL        : std_logic;
signal EUC_DIV          : std_logic;
signal EUC_FREGEF       : std_logic_vector(17 downto 0 );
signal EUC_GRRW         : std_logic;
signal EUC_GRSEL        : std_logic_vector( 3 downto 0 );
signal EUC_IDIV         : std_logic;
signal EUC_MULHL        : std_logic;
signal EUC_MULCS        : std_logic_vector( 1 downto 0 );
signal EUC_RDQUE        : std_logic;
signal EUC_REG3         : std_logic;
signal EUC_SE           : std_logic;
signal EUC_TMP2         : std_logic;
signal EUC_TMPRW        : std_logic_vector( 1 downto 0 );
signal EUC_UC           : std_logic;
signal DIVMPX_ALUCS     : std_logic_vector( 3 downto 0 );
signal DIVMPX_BUSCS     : std_logic_vector( 4 downto 0 );
signal DIVMPX_GRRW      : std_logic;
signal DIVMPX_GRSEL     : std_logic_vector( 3 downto 0 );
signal TRU_BMSBDIVREG   : std_logic;
signal TRU_BMSBTREG1    : std_logic;
signal TRU_LSBTREG2     : std_logic;
signal TRU_MSBDIVREG    : std_logic;
signal TRU_MSBPLUSREG   : std_logic;
signal TRU_MSBTREG1     : std_logic;
signal TRU_MSBTREG2     : std_logic;

component CU
	port( I_CLK         :  in std_logic;
          I_RST         :  in std_logic;
          I_MOD         :  in std_logic_vector( 1 downto 0 );
          I_RM          :  in std_logic_vector( 2 downto 0 );
		  I_BW          :  in std_logic;
          I_EA          :  in std_logic;
          I_RDQUE       :  in std_logic;
          I_D16HL       :  in std_logic;
          I_SE          :  in std_logic;
          I_TMPRW       :  in std_logic_vector( 1 downto 0 );
          I_BUSCS       :  in std_logic_vector( 4 downto 0 );
          I_GRSEL       :  in std_logic_vector( 3 downto 0 );
          I_QUEEMPTY    :  in std_logic;
          I_BDATA       :  in std_logic_vector( 7 downto 0 );
          I_BIUDATA     :  in std_logic_vector(15 downto 0 );
          O_D16HL       : out std_logic;
          O_RDQUE       : out std_logic;
          O_SE          : out std_logic;
          O_BUSCS       : out std_logic_vector( 4 downto 0 );
          O_GRSEL       : out std_logic_vector( 3 downto 0 );
          O_TMPRW       : out std_logic_vector( 1 downto 0 );
          O_BIUDATA     : out std_logic_vector(15 downto 0 );
          O_EARQ        : out std_logic;
          O_EACUSTATE_V : out std_logic_vector( 2 downto 0 )
		  ); 
end component;

component EU
	port( I_CLK       : in std_logic;
		  I_RST       : in std_logic;
          I_S77       : in std_logic;
          I_ALUCS     : in std_logic_vector( 3 downto 0 );
          I_BW        : in std_logic;
          I_BIUDATA   : in std_logic_vector(15 downto 0 );
          I_BUSCS     : in std_logic_vector( 4 downto 0 );
          I_D16HL     : in std_logic;
          I_FRSEL     : in std_logic;
          I_DIVF      : in std_logic;
          I_EA        : in std_logic;
          I_FREN      : in std_logic_vector(17 downto 0 );
          I_GRRW      : in std_logic;
          I_GRSEL     : in std_logic_vector( 3 downto 0 );
          I_MULHL     : in std_logic;
          I_QUOF      : in std_logic;
          I_TMPRW     : in std_logic_vector( 1 downto 0 );
          I_TMPCS     : in std_logic_vector( 4 downto 0 );
          I_1SETTR2   : in std_logic;
          I_ADJUST    : in std_logic_vector( 1 downto 0 );
          I_MULCS     : in std_logic_vector( 1 downto 0 );
          I_REG3      : in std_logic;
          I_SE        : in std_logic;
          I_2SETTR2   : in std_logic;
          I_USECARRY  : in std_logic;
          O_QUOF      : out std_logic;
          O_EUDATA    : out std_logic_vector(15 downto 0 );
          O_FREG      : out std_logic_vector( 8 downto 0 );
          O_SIGNDIV   : out std_logic;
          O_BSIGNDIV  : out std_logic;
          O_SIGNTR1   : out std_logic;
          O_SIGNPLS   : out std_logic;
          O_BSIGNTR1  : out std_logic;
          O_SIGNTR2   : out std_logic;
          O_LSBTR2    : out std_logic;
	      O_ALUDATA_V : out std_logic_vector(15 downto 0 );
          O_REG1      : out std_logic_vector(15 downto 0 );
          O_REG2      : out std_logic_vector(15 downto 0 );
          O_AX_V      : out std_logic_vector(15 downto 0 );
          O_BP_V      : out std_logic_vector(15 downto 0 );
          O_BX_V      : out std_logic_vector(15 downto 0 );
          O_CX_V      : out std_logic_vector(15 downto 0 );
          O_DI_V      : out std_logic_vector(15 downto 0 );
          O_DX_V      : out std_logic_vector(15 downto 0 );
          O_SI_V      : out std_logic_vector(15 downto 0 );
          O_SP_V      : out std_logic_vector(15 downto 0 )
          );
end component;

component EUC
    port( I_CLK        :  in std_logic;
          I_RST        :  in std_logic;
		  I_BDATA      :  in std_logic_vector( 7 downto 0 ); --data from que
	   	  I_QUEEMPTY   :  in std_logic; --EMPTY flag
		  I_EARQ       :  in std_logic; --END calculate EA => '1'
		  I_ENDRC      :  in std_logic; --data out flag from BIU
		  I_ENDWC      :  in std_logic; --END write memory
		  I_ENDDIV     :  in std_logic;  --end DIV => '1'
		  I_FREG       :  in std_logic_vector( 8 downto 0 ); --Flag 
		  I_DATA       :  in std_logic_vector(15 downto 0 ); --to BIU data
		  I_CX         :  in std_logic_vector(15 downto 0 ); --CX data
          I_NEXTIP     :  in std_logic_vector(15 downto 0 ); --OUT next IP data
		  I_SIGNTR1    :  in std_logic;	--for sign check(IMUL)
		  I_BSIGNTR1   :  in std_logic;	--for sign check(IMUL)
		  I_REG1       :  in std_logic_vector(15 downto 0 ); --content of the TMP1
		  I_LSBTR2     :  in std_logic;	--for MULL (1,0check)
		  O_RD         : out std_logic; --read signal to BIU
	 	  O_WR         : out std_logic; --write signal to BIU
		  O_RDQUE      : out std_logic; --read QUE signal
          O_BUSCS      : out std_logic_vector( 4 downto 0 ); --set data flow
          O_EA         : out std_logic; --calculate EA => '1'
		  O_BW         : out std_logic; --BYTE (0) or WORD (1)
          O_GRSEL      : out std_logic_vector( 3 downto 0 ); --set each GR 
		  O_MOD        : out std_logic_vector( 1 downto 0 ); --mod of OP code 
          O_RM         : out std_logic_vector( 2 downto 0 ); --rm of OP code
          O_TMPRW      : out std_logic_vector( 1 downto 0 ); --read(0) write(1) temp register 1(0) or 2(1) 
          O_ALUCS      : out std_logic_vector( 3 downto 0 ); --control ALU
          O_FRSEL      : out std_logic; --to flag reg '1'=>BUS data '0'=>ALU data
          O_FREN       : out std_logic_vector(17 downto 0);--set flag
          O_GRRW       : out std_logic; --set write(1) or read(0) GR
          O_MULHL      : out std_logic; --MUL => '1'
		  O_CSR        : out std_logic; --'1'=>SSEG from CU |'0'=>SSEG from CSEG
		  O_SRSEL      : out std_logic_vector( 1 downto 0 ); --select Segment Register(BIU)
		  O_ORPCSR     : out std_logic; --segment override prefix => '1'
		  O_ORPSRSEL   : out std_logic_vector( 1 downto 0 ); --segment register when segment override prefix
		  O_WRIP       : out std_logic; --write signal to IP
		  O_WRIR       : out std_logic; --write signal to IR
		  O_WRSR       : out std_logic; --write signal to Segment Registar(BIU)
		  O_1SETTR2    : out std_logic; --temp register2 set 1
		  O_2SETTR2    : out std_logic; --temp register2 set 2
		  O_RDSR       : out std_logic; --read segment REG (write to mem)
		  O_IO         : out std_logic; --access I/O device
		  O_OADR       : out std_logic_vector(15 downto 0); --address when access I/O device 
		  O_RDIR       : out std_logic; --read IR
		  O_DIV        : out std_logic; --divid => '1'
		  O_IDIV       : out std_logic; --integer divid => '1',normal divid => '0'
		  O_EAPLUS2    : out std_logic; --to BIU (EA+2)
		  O_MDTF       : out std_logic; --'1' => REGDT <= MEMORY DATA
		  O_REG3       : out std_logic;  --'1' => use tmp3 
		  O_DATA       : out std_logic_vector(15 downto 0 ); --Out EUC data
		  O_2EU        : out std_logic;  --Set EUC data to EU signal
          O_2BIU       : out std_logic;  --Set EUC data to BIU signal
		  O_2SR        : out std_logic;  --Seg EUC data(address) to Segment Register
		  O_USECARRY   : out std_logic;  --use carry frag
		  O_ADJUST     : out std_logic_vector( 1 downto 0);
		  O_HLT        : out std_logic;  --HALT => '1'
		  O_WRPLUS     : out std_logic;  --plus write signal
          O_PLUSOP     : out std_logic_vector( 2 downto 0); --+1,+2,+3,+4,
		  O_PLUSMOD    : out std_logic_vector( 1 downto 0); --+1,+2,
		  O_QUERST     : out std_logic; --Reset QUE signal => '1'
		  O_EUCRST     : out std_logic; --OEUC Reset signal
		  O_ADROUT     : out std_logic; --address out memory