mpx2in1outa.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MPX2IN1OUTA is
	generic( IDW0 : integer ;
			 IDW1 : integer ; --memory WORD
			 ODW  : integer 
			 ); 
	port( I_SW     :  in std_logic;    
		  I_DATA01 :  in std_logic_vector( IDW0-1 downto 0 ); --I_EN=0
          I_DATA11 :  in std_logic_vector( IDW1-1 downto 0 ); --I_EN=1
          O_DATA   : out std_logic_vector( ODW-1  downto 0 )
		  );  
end MPX2IN1OUTA;

architecture RTL of MPX2IN1OUTA is
begin
	process (I_SW,I_DATA01,I_DATA11)
	begin
		if (I_SW = '1') then
			O_DATA <= "00000000"&I_DATA11;
		else
			O_DATA <= I_DATA01;
		end if;
	end process;
end RTL;