mpx12in6out.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MPX12IN6OUT is
	generic( --S1W : integer :=  1; 
			 --S2W : integer :=  1;
			 --S3W : integer :=  1;
			 S4W : integer :=  2;
			 S5W : integer :=  4;
			 S6W : integer :=  5
			 ); 
	port( I_SW     :  in std_logic;
		  I_DATA11 :  in std_logic;           
		  I_DATA12 :  in std_logic;
          I_DATA13 :  in std_logic;
          I_DATA14 :  in std_logic_vector(S4W-1 downto 0 );
		  I_DATA15 :  in std_logic_vector(S5W-1 downto 0 );
		  I_DATA16 :  in std_logic_vector(S6W-1 downto 0 );
          I_DATA01 :  in std_logic;
          I_DATA02 :  in std_logic;
          I_DATA03 :  in std_logic;
          I_DATA04 :  in std_logic_vector(S4W-1 downto 0 );
		  I_DATA05 :  in std_logic_vector(S5W-1 downto 0 );
		  I_DATA06 :  in std_logic_vector(S6W-1 downto 0 );
          O_DATA1  : out std_logic;
          O_DATA2  : out std_logic;
          O_DATA3  : out std_logic;
	   	  O_DATA4  : out std_logic_vector(S4W-1 downto 0);
	      O_DATA5  : out std_logic_vector(S5W-1 downto 0);
          O_DATA6  : out std_logic_vector(S6W-1 downto 0)
		  );
end MPX12IN6OUT;

architecture RTL of MPX12IN6OUT is
begin
	process(I_SW,I_DATA11,I_DATA12,I_DATA13,I_DATA14,I_DATA15,I_DATA16,
			I_DATA01,I_DATA02,I_DATA03,I_DATA04,I_DATA05,I_DATA06)
	begin
		if (I_SW = '1') then
			O_DATA1 <= I_DATA11;
            O_DATA2 <= I_DATA12;
			O_DATA3 <= I_DATA13;
			O_DATA4 <= I_DATA14;
			O_DATA5 <= I_DATA15;
			O_DATA6 <= I_DATA16;
 	    else
			O_DATA1 <= I_DATA01;
			O_DATA2 <= I_DATA02;
			O_DATA3 <= I_DATA03;
			O_DATA4 <= I_DATA04;
			O_DATA5 <= I_DATA05;
			O_DATA6 <= I_DATA06;
		end if;
	end process;

end RTL;