cseg.vhd

X8086的VHDL源码

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--   FILE NAME : CSEG_REG.vhd
--   FUNCTION  : control select segment signal
--   AUTHOR    : Kazuma Mishima
--   DATE      : 9/2001
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.UPAC.all;

entity CSEG is
	port( I_RM        :  in std_logic_vector( 2 downto 0); --r/m from CU
          I_MOD       :  in std_logic_vector( 1 downto 0); --MOD from CU
          I_CSR       :  in std_logic; --'1'=>SSEG from CU |'0'=>SSEG from CSEG 
		  I_SRSEL     :  in std_logic_vector( 1 downto 0); --when STRING,STACK, assignment SSEG
		  I_ORPCSR    :  in std_logic; --override prefix => '1'
		  I_ORPSRSEL  :  in std_logic_vector( 1 downto 0); --segment register when override prefix
          O_SRSEL     : out std_logic_vector( 1 downto 0) --select segment signal
		  ); 
end CSEG;

architecture RTL of CSEG is
begin
	process(I_CSR,I_SRSEL,I_RM,I_MOD,I_ORPCSR,I_ORPSRSEL)
	begin
		if ((I_CSR = '0' and I_ORPCSR = '0') and ((I_RM(2 downto 1) = "01" and (not I_MOD = "11"))or
		    (I_RM = "110" and I_MOD = "01")or(I_RM = "110" and I_MOD = "10")))then --when base registar => BP
			O_SRSEL <= SS; --assignment SS 
		elsif (I_CSR = '1' and I_ORPCSR='0') then --when STRING,STACK
			O_SRSEL <= I_SRSEL; --out SSEG from CU
		elsif (I_ORPCSR = '1')then
			O_SRSEL <= I_ORPSRSEL;
		else
			O_SRSEL <= DS; --assignemnt DS
		end if;
	end process;

end RTL;