divcu.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library synplify;
use synplify.attributes.all;
  
entity DIVCU is
	port( I_CLK      :  in std_logic;
          I_RST      :  in std_logic;    
          I_DIV      :  in std_logic;
          I_IDIV     :  in std_logic;
          I_QUOF     :  in std_logic;
          I_AAM      :  in std_logic;
          I_BW       :  in std_logic;
          I_MOD      :  in std_logic_vector( 1 downto 0 );
          I_RM       :  in std_logic_vector( 2 downto 0 );
          I_BSIGNDIV :  in std_logic;
          I_SIGNDIV  :  in std_logic;
          I_SIGNPLS  :  in std_logic;
          I_SIGNTR2  :  in std_logic;
          O_TMPCS    : out std_logic_vector( 4 downto 0 );
          O_BUSCS    : out std_logic_vector( 4 downto 0 );
          O_GRSEL    : out std_logic_vector( 3 downto 0 );
          O_GRRW     : out std_logic;
          O_QUOF     : out std_logic;
          O_DIVF     : out std_logic;
          O_ENDDIV   : out std_logic;
          O_DIVSTATE : out std_logic_vector( 3 downto 0 );
          O_TYPEZERO : out std_logic
		  );
end DIVCU;
  
use work.all;
architecture RTL of DIVCU is
 
signal DIVCOUNT_DIVCOUNT   : std_logic_vector( 4 downto 0 );
signal DIVCOUNT_LOOPEND : std_logic;
signal DIVDEC_NEGA      : std_logic;
signal DIVDEC_SCOUNT    : std_logic;
signal DIVFSM_DIVSTATE  : std_logic_vector( 3 downto 0 );

component DIVCOUNT
    port( I_CLK      :  in std_logic;
          I_RST      :  in std_logic;
          I_BW       :  in std_logic;
		  I_SCOUNT	 :  in std_logic;
		  O_DIVCOUNT : out std_logic_vector(4 downto 0);
          O_LOOPEND  : out std_logic
		  );
end component;

component DIVDEC
    port( I_CLK       :  in std_logic;
		  I_RST       :  in std_logic;
		  I_DIVSTATE  :  in std_logic_vector( 3 downto 0);
          I_BW        :  in std_logic;
          I_RM        :  in std_logic_vector( 2 downto 0);
          I_MOD       :  in std_logic_vector( 1 downto 0);
          I_AAM       :  in std_logic; --control signal for AAM
          I_QUOF      :  in std_logic;
		  I_IDIV	  :  in std_logic;	--signed div(idiv)
		  I_DIVCOUNT  :  in std_logic_vector( 4 downto 0);
		  I_SIGNPLS   :  in std_logic; --for idiv
		  I_SIGNTR2   :  in std_logic; --for idiv
		  I_SIGNDIV   :  in std_logic; --for idiv
		  I_BSIGNDIV  :  in std_logic; --for idiv
		  O_TMPCS     : out std_logic_vector( 4 downto 0);	--for div tmpcs           
          O_BUSCS     : out std_logic_vector( 4 downto 0);
          O_GRRW      : out std_logic;
          O_GRSEL     : out std_logic_vector( 3 downto 0);
          O_DIVF      : out std_logic;           
          O_QUOF      : out std_logic;
		  O_ENDDIV    : out std_logic; --for div end(<=1)
		  O_NEGA	  : out std_logic; --signset for answer
		  O_SCOUNT	  : out std_logic;
		  O_TYPEZERO  : out std_logic; --type0 interrupt
          O_DIVSTATE  : out std_logic_vector( 3 downto 0) --for test 
		  );
end component;

component DIVFSM
	port( I_CLK      :  in std_logic;
		  I_RST      :  in std_logic;
		  I_BW       :  in std_logic;
		  I_LOOPEND  :  in std_logic;
          I_DIV      :  in std_logic;
          I_NEGA     :  in std_logic;
          O_DIVSTATE : out std_logic_vector( 3 downto 0 )
          ); 
end component; 

begin 

	DIVCOUNT_DIVCU : DIVCOUNT
    port map( 
		I_CLK => I_CLK,
        I_RST => I_RST,
        I_BW => I_BW,
		I_SCOUNT => DIVDEC_SCOUNT,
		O_DIVCOUNT => DIVCOUNT_DIVCOUNT,
        O_LOOPEND => DIVCOUNT_LOOPEND
		);

	DIVDEC_DIVCU : DIVDEC
    port map( 
		I_CLK => I_CLK,
		I_RST => I_RST,
		I_DIVSTATE => DIVFSM_DIVSTATE,
        I_BW => I_BW,
        I_RM => I_RM,
        I_MOD => I_MOD,
        I_AAM => I_AAM,
        I_QUOF => I_QUOF,
		I_IDIV => I_IDIV,
		I_DIVCOUNT => DIVCOUNT_DIVCOUNT,
		I_SIGNPLS => I_SIGNPLS,  
		I_SIGNTR2 => I_SIGNTR2,
		I_SIGNDIV => I_SIGNDIV,
		I_BSIGNDIV => I_BSIGNDIV,
		O_TMPCS => O_TMPCS, 
        O_BUSCS => O_BUSCS,
        O_GRRW => O_GRRW,
        O_GRSEL => O_GRSEL,
        O_DIVF => O_DIVF,
        O_QUOF => O_QUOF,
		O_ENDDIV => O_ENDDIV,
		O_NEGA => DIVDEC_NEGA,
		O_SCOUNT => DIVDEC_SCOUNT, 
		O_TYPEZERO => O_TYPEZERO,
        O_DIVSTATE => O_DIVSTATE
		);
 
	DIVFSM_DIVCU : DIVFSM
	port map( 
        I_CLK => I_CLK,
		I_RST => I_RST,
		I_BW => I_BW,
		I_LOOPEND => DIVCOUNT_LOOPEND,
        I_DIV => I_DIV,
        I_NEGA => DIVDEC_NEGA ,
        O_DIVSTATE => DIVFSM_DIVSTATE
        ); 

end RTL;