mcu.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.UPAC.ALL;

entity MCU is
	generic( MADRWIDTH : integer  --memory WORD
			 ); 
    Port( I_CLK     :  in std_logic;
		  I_RST     :  in std_logic;
		  I_ALE     :  in std_logic; --address latch signal
	      I_A19A16  :  in std_logic_vector( 3 downto 0 ); --address 19bit~16bit
		  I_EXTBUS  :  in std_logic_vector(15 downto 0 );
          I_WR_N    :  in std_logic; --when write => 'L'
          I_RD_N    :  in std_logic; --when read => 'L'           
          I_BHE     :  in std_logic; --from DC BHE signal
		  I_DATAH   :  in std_logic_vector( 7 downto 0 ); --from memory DATA High
          I_DATAL   :  in std_logic_vector( 7 downto 0 ); --from memory DATA Low
		  O_WRH     : out std_logic; --High memory write signal (write => '1')
		  O_WRL     : out std_logic; --Low memory write signal (write => '1')
          O_DATAH   : out std_logic_vector( 7 downto 0 ); --write memory data High
          O_DATAL   : out std_logic_vector( 7 downto 0 ); --write memory data Low
          O_ADR     : out std_logic_vector(MADRWIDTH-1 downto 0 ); --memory address
		  O_EXTBUS  : out std_logic_vector(15 downto 0 )
		  );  
end MCU;

architecture RTL of MCU is

signal adr : std_logic_vector(19 downto 0); --address latch

begin   
--address latch
	process(I_RST,I_CLK,I_ALE,I_A19A16,I_EXTBUS)
	begin
		if    (I_RST = RST_ACT) then
			adr <= "00000000000000000000";
		elsif (I_CLK'event and I_CLK = '0') then
			if (I_ALE='1')then
				adr <= I_A19A16(3 downto 0) & I_EXTBUS(15 downto 0);
			end if;
		end if;
	end process;

	process(I_RST,I_CLK,I_ALE,I_EXTBUS)
	begin
		if    (I_RST = RST_ACT) then
			O_ADR <= (others=>'0');
		elsif (I_CLK'event and I_CLK = '0') then
			if(I_ALE='1')then
				O_ADR <= I_EXTBUS(MADRWIDTH downto 1);
			end if;
		end if;
	end process;

--write signal,read signal
	process(I_EXTBUS)
	begin     
		O_DATAH <= I_EXTBUS(15 downto 8);    
		O_DATAL <= I_EXTBUS(7 downto 0);
	end process;

	process(adr,I_WR_N,I_RD_N,I_BHE)
	begin
	    --write signal
		if(I_WR_N='0' and I_RD_N='1')then --when out data to write memory             
			if   (I_BHE='0' and adr(0)='0')then --BHE='0',A0='0' => D15~D0
				O_WRH <= '1';
				O_WRL <= '1';
			elsif(I_BHE='1' and adr(0)='0')then --BHE='1',A0='0' => D7~D0
				O_WRH <= '0';
				O_WRL <= '1';
			elsif(I_BHE='0' and adr(0)='1')then --BHE='0',A0='1' => D15~D8
				O_WRH <= '1';
				O_WRL <= '0';
			else
				O_WRH <= '0';
				O_WRL <= '0';	  		
			end if;
		else
			O_WRH <= '0';
			O_WRL <= '0';
		end if;
	end process;

	process(I_DATAH,I_DATAL)
	begin
		O_EXTBUS <= I_DATAH & I_DATAL;
	end process;
			    
end RTL;